PIC18F2439T-I/SO Microchip Technology, PIC18F2439T-I/SO Datasheet - Page 95
![IC MCU FLASH 6KX16 EE A/D 28SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
PIC18F2439T-I/SO
Manufacturer Part Number
PIC18F2439T-I/SO
Description
IC MCU FLASH 6KX16 EE A/D 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2439-ISO.pdf
(322 pages)
3.PIC18F2439-ISO.pdf
(6 pages)
4.PIC18F2439-ISO.pdf
(34 pages)
Specifications of PIC18F2439T-I/SO
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
12KB (6K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
640 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
640 B
Interface Type
I2C, SPI, AUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Number Of Timers
16 bit
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
DV164005, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
5 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC18F2439-ISO PDF datasheet #2
- PIC18F2439-ISO PDF datasheet #3
- PIC18F2439-ISO PDF datasheet #4
- Current page: 95 of 322
- Download datasheet (7Mb)
9.5
This section is only applicable to the PIC18F4X39
devices.
PORTE is a 3-bit wide, bi-directional port. The corre-
sponding Data Direction register is TRISE. Setting a
TRISE bit (= 1) will make the corresponding PORTE pin
an input (i.e., put the corresponding output driver in a
High Impedance mode). Clearing a TRISE bit (= 0) will
make the corresponding PORTE pin an output (i.e., put
the contents of the output latch on the selected pin).
The Data Latch register (LATE) is also memory
mapped. Read-modify-write operations on the LATE
register reads and writes the latched output value for
PORTE.
PORTE has three pins (RE0/AN5/RD, RE1/AN6/WR
and RE2/AN7/CS) which are individually configurable
as inputs or outputs. These pins have Schmitt Trigger
input buffers.
Register 9-1 shows the TRISE register, which also
controls the parallel slave port operation.
PORTE pins are multiplexed with analog inputs. When
selected as an analog input, these pins will read as '0's.
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
EXAMPLE 9-5:
2002 Microchip Technology Inc.
CLRF
CLRF
MOVLW
MOVWF
MOVLW
MOVWF
Note:
PORTE, TRISE and LATE
Registers
PORTE
LATE
0x07
ADCON1
0x05
TRISE
On a Power-on Reset, these pins are
configured as analog inputs.
; Initialize PORTE by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Configure A/D
; for digital inputs
; Value used to
; initialize data
; direction
; Set RE<0> as inputs
; RE<1> as outputs
; RE<2> as inputs
INITIALIZING PORTE
Preliminary
FIGURE 9-9:
WR TRISE
RD LATE
Data
Bus
WR LATE
or PORTE
RD TRISE
RD PORTE
To Analog Converter
Note 1:
I/O pins have diode protection to V
TRIS Latch
Data Latch
D
D
CK
CK
Q
Q
PIC18FXX39
PORTE BLOCK DIAGRAM
IN I/O PORT MODE
Q
EN
EN
D
Schmitt
Trigger
Input
Buffer
DS30485A-page 93
DD
and V
I/O pin
SS
.
(1)
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