PIC18F8620T-E/PT Microchip Technology, PIC18F8620T-E/PT Datasheet - Page 32
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18F8620T-E/PT
Manufacturer Part Number
PIC18F8620T-E/PT
Description
IC PIC MCU FLASH 32KX16 80TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F8520T-IPT.pdf
(380 pages)
3.PIC18F8520T-IPT.pdf
(40 pages)
4.PIC18F6620-IPT.pdf
(14 pages)
5.PIC18F6620-IPT.pdf
(12 pages)
Specifications of PIC18F8620T-E/PT
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.75K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
80-TFQFP
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3840 B
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
68
Number Of Timers
2 x 8 bit
Operating Supply Voltage
4.2 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183022, DM183032
Minimum Operating Temperature
- 40 C
On-chip Adc
16 bit
Data Rom Size
1024 B
Height
1 mm
Length
12 mm
Supply Voltage (max)
5.5 V, 5.8 V
Supply Voltage (min)
3.9 V, 4.2 V
Width
12 mm
For Use With
XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F8620T-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18F8520T-IPT PDF datasheet #2
- PIC18F8520T-IPT PDF datasheet #3
- PIC18F6620-IPT PDF datasheet #4
- PIC18F6620-IPT PDF datasheet #5
- Current page: 32 of 380
- Download datasheet (7Mb)
PIC18F6520/8520/6620/8620/6720/8720
3.1
A Power-on Reset pulse is generated on-chip when
V
circuitry, tie the MCLR pin through a 1 k
resistor to V
components usually needed to create a Power-on
Reset delay. A minimum rise rate for V
(parameter D004). For a slow rise time, see Figure 3-2.
When the device starts normal operation (i.e., exits the
Reset condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
FIGURE 3-2:
3.2
The Power-up Timer provides a fixed nominal time-out
(parameter #33) only on power-up from the POR. The
Power-up Timer operates on an internal RC oscillator.
The chip is kept in Reset as long as the PWRT is active.
The PWRT’s time delay allows V
able level. A configuration bit is provided to enable/
disable the PWRT.
The power-up time delay will vary from chip-to-chip due
to V
parameter #33 for details.
DS39609B-page 30
DD
Note 1: External Power-on Reset circuit is required
DD
rise is detected. To take advantage of the POR
, temperature and process variation. See DC
Power-on Reset (POR)
Power-up Timer (PWRT)
2: R < 40 k is recommended to make sure that
3: R1 = 1 k to 10 k will limit any current flow-
D
only if the V
The diode D helps discharge the capacitor
quickly when V
the voltage drop across R does not violate
the device’s electrical specification.
ing into MCLR from external capacitor C, in
the event of MCLR/V
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).
DD
V
. This will eliminate external RC
DD
R
C
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW V
DD
DD
R1
power-up slope is too slow.
powers down.
PP
DD
DD
PIC18FXX20
pin breakdown due to
MCLR
to rise to an accept-
POWER-UP)
DD
is specified
to 10 k
3.3
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycles (from OSC1 input) delay after the
PWRT delay is over (parameter #32). This ensures that
the crystal oscillator or resonator has started and
stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset, or wake-up from
Sleep.
3.4
With the PLL enabled, the time-out sequence following
a Power-on Reset is different from other oscillator
modes. A portion of the Power-up Timer is used to
provide a fixed time-out that is sufficient for the PLL to
lock to the main oscillator frequency. This PLL lock
time-out (T
oscillator start-up time-out.
3.5
A configuration bit, BOREN, can disable (if clear/
programmed), or enable (if set) the Brown-out Reset
circuitry. If V
than parameter #35, the brown-out situation will reset
the chip. A Reset may not occur if V
parameter D005 for less than parameter #35. The chip
will remain in Brown-out Reset until V
BV
invoked after V
the chip in Reset for an additional time delay (parame-
ter #33). If V
Timer is running, the chip will go back into a Brown-out
Reset and the Power-up Timer will be initialized. Once
V
execute the additional time delay.
3.6
On power-up, the time-out sequence is as follows:
First, PWRT time-out is invoked after the POR time
delay has expired. Then, OST is activated. The total
time-out will vary based on oscillator configuration and
the status of the PWRT. For example, in RC mode with
the PWRT disabled, there will be no time-out at all.
Figures 3-3 through 3-7 depict time-out sequences on
power-up.
Since the time-outs occur from the POR pulse, the
time-outs will expire if MCLR is kept low long enough.
Bringing MCLR high will begin execution immediately
(Figure 3-5). This is useful for testing purposes, or to
synchronize more than one PIC18FXX20 device
operating in parallel.
Table 3-2 shows the Reset conditions for some Special
Function Registers, while Table 3-3 shows the Reset
conditions for all of the registers.
DD
DD
. If the Power-up Timer is enabled, it will be
rises above BV
Oscillator Start-up Timer (OST)
PLL Lock Time-out
Brown-out Reset (BOR)
Time-out Sequence
PLL
DD
DD
) is typically 2 ms and follows the
DD
falls below parameter D005 for greater
drops below BV
rises above BV
DD
2004 Microchip Technology Inc.
, the Power-up Timer will
DD
DD
while the Power-up
; it then will keep
DD
DD
rises above
falls below
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