SX28AC-I/DP Parallax Inc, SX28AC-I/DP Datasheet
SX28AC-I/DP
Specifications of SX28AC-I/DP
Related parts for SX28AC-I/DP
SX28AC-I/DP Summary of contents
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... SX20AC/SX28AC Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability and On-Chip Debug 1.0 PRODUCT OVERVIEW 1.1. Introduction The Parallax SX family of configurable communications controllers is fabricated in an advanced CMOS process technology. The advanced process, combined with a RISC-like architecture, allows high-speed computation, flexible I/O control, and efficient data manipulation ...
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... DC Characteristics................................................................... 41 17.3. AC Characteristics ................................................................... 42 17.4. Comparator DC and AC Specifications.................................... 42 17.5. Typical Performance Characteristics (25°C) ............................ 43 18.0 Package Dimensions..................................................46 18.1. SX20AC/SS ............................................................................. 46 18.2. SX28AC/SS ............................................................................. 47 18.3. SX28AC/DP............................................................................. 48 19.0 Manufacturing Information ........................................49 19.1. Reflow Peak Temperature ....................................................... 49 19.2. MSL3 Compliance ................................................................... 49 19.3. Green/RoHS Compliance ........................................................ 49 19.4. Stress Testing Data Summary ................................................. 49 Page www ...
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... Parallax SX20AC/SX28AC 1.2. Key Features 75 MIPS Performance • SX20AC/SX28AC MHz • SX20AC/SX28AC: as low as 13.3 ns instruction cycle, 39.9 ns internal interrupt response • 1 instruction per clock for most instructions (skips require 2 clocks, branches require 3 clocks, IREAD requires 4) EE/FLASH Program Memory and SRAM Data Memory • ...
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... SX’s deterministic timing. The primary technical resources for programming the SX in assembly language include the following: • The SX20AC/SX28AC datasheet • SX-Key Development System User’s Manual by Parallax, Inc. • Programming the SX Microcontroller – A Complete ...
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... Parallax SX20AC/SX28AC 1.8. Part Numbering Device Part# Pins I/O SX20AC/ SX20AC/SS-G SX28AC/ SX28AC/DP-G SX28AC/ SX28AC/SS-G * Ratings are preliminary © Parallax Inc. Table 1-1: Part Numbering EE/Flash RAM Voltage (Words) (Bytes) Range (V) 3.0 – 5.5 2K 137 3.0 – 5.5 2K 136 3.0 – 5.5 ...
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... Parallax SX20AC/SX28AC 2.0 CONNECTION DIAGRAMS 2.1. Pin Assignments 2.2. Pin Descriptions Name Pin Type Input Levels RA0 I/O TTL/CMOS RA1 I/O TTL/CMOS RA2 I/O TTL/CMOS RA3 I/O TTL/CMOS RB0 I/O TTL/CMOS/ST RB1 I/O TTL/CMOS/ST RB2 I/O TTL/CMOS/ST RB3 I/O TTL/CMOS/ST RB4 ...
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... Parallax SX20AC/SX28AC 2.3. Typical Connection Diagrams Note: The 10 kΩ resistor connected to the MCLR pin is not needed when controlled externally. Note: The 10 kΩ resistor connected to the MCLR pin is not needed when controlled externally. © Parallax Inc. Page www.parallax.com Rev 1.6 11/20/2006 ...
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... Parallax SX20AC/SX28AC Typical Connection Diagrams (continued) Note: The 10 kΩ resistor connected to the MCLR pin is not needed when controlled externally. © Parallax Inc. Page www.parallax.com Rev 1.6 11/20/2006 ...
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... Parallax SX20AC/SX28AC 3.0 PORT DESCRIPTIONS All models contain a 4-bit I/O port (Port A), an 8-bit I/O port (Port B). The SX28 also contains a second 8-bit I/O port (Port C). Port A provides symmetrical drive capability. Each port has three associated 8-bit registers (Direction, Data, TTL/CMOS Select, and Pull-Up Enable) ...
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... Parallax SX20AC/SX28AC For example, suppose all four Port A pins are configured as outputs and you wish to set RA0 and RA1 high, and RA2 and RA3 low: mov W,#$03 ;load W with the value 03h ;(bits 0 and 1 high) mov $05,W ;write 03h to Port A data ...
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... Parallax SX20AC/SX28AC 3.1.1. Read-Modify-Write Considerations Caution must be exercised when performing two successive read-modify-write instructions (SETB or CLRB operations I/O port pin. Input data used for an instruction must be valid during the time the instruction is executed, and the output result from an instruction is valid only after that instruction completes its operation ...
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... Parallax SX20AC/SX28AC PLP_A, PLP_B, and PLP_C: Pullup Enable Registers (MODE=0Eh) Each register bit determines whether an internal pullup resistor is connected to the pin. Set the bit disconnect the pullup resistor or clear the bit connect the pullup resistor. LVL_A, LVL_B, and LVL_C: Input Level Registers ...
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... Parallax SX20AC/SX28AC 4.0 SPECIAL-FUNCTION REGISTERS The CPU uses a set of special-function registers to control the operation of the device. The CPU registers include an 8-bit working register (W), which serves as a pseudo accumulator. It holds the second operand of an instruction, receives the literal in immediate type instructions, and also can be program selected as the destination register ...
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... Parallax SX20AC/SX28AC 4.3. OPTION Register RTW RTW_IE RTS RTE_ES PSA Bit 7 When the OPTIONX bit in the FUSE word is cleared, bits 7 and 6 of the OPTION register function as described below. When the OPTIONX bit is set, bits 7 and 6 of the OPTION register read as ‘1’s. ...
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... Parallax SX20AC/SX28AC 5.0 DEVICE CONFIGURATION REGISTERS The SX device has three registers (FUSE, FUSEX, DEVICE) that control functions such as operating the device in Turbo mode, extended (8-level deep) stack operation, and speed selection for the internal RC oscillator. These registers are not programmable “on the 5 ...
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... Parallax SX20AC/SX28AC 5.2. FUSEX Word (Read/Program via Programming Command) IRCTRIM2 PINS IRCTRIM1 IRCTRIM0 Bit 11 IRCTRIM2: Internal RC oscillator trim bits. This 3-bit field adjusts the operation of the internal RC oscillator to make it IRCTRIM 0 operate within the target frequency range 4 MHz plus or minus 8%. Parts are shipped from the factory untrimmed ...
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... Parallax SX20AC/SX28AC 6.0 MEMORY ORGANIZATION 6.1. Program Memory The program memory is organized as 2K, 12-bit wide words. The program memory words are addressed sequentially by a binary program counter. The program counter starts at zero. If there is no branch operation, it will increment to the maximum value possible for the device and roll over and begin again ...
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... Parallax SX20AC/SX28AC © Parallax Inc. Figure 6-1: Data Memory Organization Page www.parallax.com Rev 1.6 11/20/2006 ...
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... Parallax SX20AC/SX28AC 7.0 POWER DOWN MODE The power down mode is entered by executing the SLEEP instruction. In power down mode, only the Watchdog Timer (WDT) is active. If the Watchdog Timer is enabled, upon execution of the SLEEP instruction, the Watchdog Timer is cleared, the TO (time out) bit is set in the STATUS register, and the PD (power down) bit is cleared in the STATUS register ...
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... Parallax SX20AC/SX28AC 7.2. Port B MIWU/Interrupt Configuration The WKPND_B register comes up with an unknown value upon reset. The user program must clear the register prior to enabling the wake-up condition or interrupts. The proper initialization sequence is: 1. Select the desired edge (through WKED_B register). 2. Clear the WKPND_B register. ...
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... Parallax SX20AC/SX28AC 8.0 INTERRUPT SUPPORT The device supports both internal and external maskable interrupts. The internal interrupt is generated as a result of the RTCC rolling over from 0FFh to 00h. This interrupt source has an associated enable bit located in the OPTION register. There is no pending bit associated with this interrupt ...
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... Parallax SX20AC/SX28AC All interrupts are global in nature; that is, no interrupt has priority over another. Interrupts are handled sequentially. Figure 8-2 shows the interrupt processing sequence. Once an interrupt is acknowledged, all subsequent global interrupts are disabled until return from servicing the current interrupt. The PC is pushed onto the single level ...
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... Parallax SX20AC/SX28AC 9.0 OSCILLATOR CIRCUITS The device supports several user-selectable oscillator modes. The oscillator modes are selected by programming the appropriate values into the FUSE Word register. These are the different oscillator modes offered: LP: Low Power Crystal XT: Crystal/Resonator HS: High Speed Crystal/Resonator RC: External Resistor/Capacitor 9 ...
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... Parallax SX20AC/SX28AC Table 9-2: External Component Selection for Murata Ceramic Resonators (V FOSC2:FOSC0 Frequency 011 4 MHz CSA4.00MG 011 4 MHz CST4.00MGW 011 4 MHz CSTCC4.00G0H6 011 8 MHz CSA8.00MTZ 011 8 MHz CST8.00MTW 011 8 MHz CSTCC8.00MG0H6 011 20 MHz CSA20.00MXZ040 011 20 MHz CST20.00MXW0H1 011 20 MHz CSACV20.00MXJ040 011 20 MHz CSTCV20 ...
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... SX, we have specified a custom TTL oscillator that performs well throughout the industrial temperature range. Figure 9-3 depicts how the SX is used with the Transko 75MHz TTL oscillator. Figure 9-3: SX28AC/DP with 75 MHz TTL Oscillator 9.3. External RC Mode The external RC oscillator mode provides a cost-effective approach for applications that do not require a precise operating frequency ...
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... Parallax SX20AC/SX28AC 10.0 REAL TIME CLOCK (RTCC)/WATCHDOG TIMER The device contains an 8-bit Real Time Clock/Counter (RTCC) and an 8-bit Watchdog Timer (WDT). An 8-bit programmable prescaler extends the RTCC to 16 bits. If the prescaler is not used for the RTCC, it can serve as a postscaler for the Watchdog Timer. Figure 10-1 shows the RTCC and WDT block diagram ...
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... Parallax SX20AC/SX28AC 11.0 COMPARATOR The device contains an on-chip differential comparator. Ports RB0-RB2 support the comparator. Ports RB1 and RB2 are the comparator negative and positive inputs, respectively, while Port RB0 serves as the comparator output pin. To use these pins in conjunction with the comparator, the user program must configure Ports RB1 and RB2 as inputs and Port RB0 as an output ...
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... Parallax SX20AC/SX28AC 12.0 RESET Power-On Reset, Brown-Out Reset, Watchdog Reset, or External Reset initializes the device. Each one of these reset conditions causes the program counter to branch to the top of the program memory. For example, on the device with 2048 K ($800 hex) words of program memory, the program counter is initialized to 07FF upon a valid reset condition ...
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... Parallax SX20AC/SX28AC Figure 12-3 shows the on-chip Power-On Reset sequence where the MCLR pin is tied Note: connecting the MCLR pin directly to the V supply is not recommended. If the V before the DRT timeout period expires, the device will receive a proper reset. However, Figure 12-4 depicts a situation where V rises too slowly ...
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... Parallax SX20AC/SX28AC 14.0 REGISTER STATES UPON DIFFERENT RESET OPERATIONS The effect of different reset operation on a register depends on the register and the type of reset operation. Some registers are initialized to specific values, some are left unchanged, some are undefined, and some are initialized to an unknown value. A register that starts with ...
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... Parallax SX20AC/SX28AC 15.0 INSTRUCTION SET As mentioned earlier, the SX family of devices uses a modified Harvard architecture with memory-mapped input/output. The device also has a RISC type architecture in that there are 43 single-word basic instructions. The instruction set contains byte-oriented file register, bitoriented file register, and literal/control instructions. ...
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... Parallax SX20AC/SX28AC 15.4. RAM Addressing Direct Addressing The FSR register must initialized with an appropriate value in order to address the desired RAM register. The following table and code example show how to directly access the banked registers. Bank mov FSR,#$070 ;Select RAM Bank 3 ...
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... Parallax SX20AC/SX28AC 15.10.1. Jump Operation When a JMP instruction is executed, the lower nine bits of the program counter is loaded with the address of the specified label. The upper two bits of the program counter are loaded with the page select bits, PA1:PA0, contained in the STATUS register. Therefore, care must be exercised to ensure the page select bits are pointing to the correct page before the jump occurs ...
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... Parallax SX20AC/SX28AC 15.12.2. Pop Operation When a return instruction is executed the subroutine stack is popped. Specifically, the contents of Stack 1 are copied into the program counter and the contents of each stack level are moved to the next higher level. For example, Stack 1 receives the contents of Stack 2, etc., until Stack 7 is overwritten with the contents of Stack 8 ...
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... Parallax SX20AC/SX28AC 16.0 NATIVE SX INSTRUCTION SET SUMMARY TABLES Table 16-1 through Table 16-6 list all of the native assembly instructions, organized by category. For each instruction, the table shows the instruction mnemonic (as written in assembly language), a brief description of what the instruction does, the number of instruction cycles required for execution, the binary opcode, and the status bits affected by the instruction ...
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... Parallax SX20AC/SX28AC Table 16-2: Native Mnemonic, Description Operands Add ( W); carry bit is added if CF ADD fr,W bit in FUSEX register is cleared to 0 Add +fr); carry bit is added if CF ADD W,fr bit in FUSEX register is cleared to 0 CLR fr Clear fr ( CLR W Clear Clear Watchdog Timer, clear prescaler if ...
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... Parallax SX20AC/SX28AC Table 16-4: Mnemonic, Description Operands MOV fr,W Move ( MOV W,fr Move fr) Move (fr- fr-W); complement of MOV W,fr-W carry bit is subtracted if CF bit in FUSEX register is cleared to 0 MOV W,#lit Move Literal lit) MOV W,/fr Move Complement FFh) MOV W,--fr Move (fr – – 1) ...
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... Parallax SX20AC/SX28AC Table 16-5: SX Instruction Set: Program Control Instructions Mnemonic, Description Operands Call Subroutine: Top-of-stack = program counter + 1 CALL addr8 PC(7:0) = addr8 Program counter ( Program counter (10:9) = PA1:PA0 Jump to Address: PC(7:0) = addr9(7:0) JMP addr8 Program counter = (8) = addr9(8) Program counter (10:9) = PA1:PA0 NOP ...
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... Parallax SX20AC/SX28AC 16.1. Equivalent Assembler Mnemonics Some assemblers support additional mnemonics that are special cases of existing instructions or alternative mnemonics for standard ones. For example, an assembler might support the mnemonic “CLC” (clear Table 16-7: SX Equivalent Assembler Mnemonics Syntax CLC Clear Carry bit ...
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... Parallax SX20AC/SX28AC 17.0 ELECTRICAL CHARACTERISTICS 17.1. Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the remainder of Section 17 ...
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... Parallax SX20AC/SX28AC 17.2. DC Characteristics SX20/28AC at 75MHz(Temp Range: 0°C <= Ta <= +70°C) SX20/28AC at 50MHz (Temp Range: -40°C <= Ta <= +85°C) Symbol Parameter Supply Voltage (Note rise rate (Note 1) Vdd dd Supply Current, active I dd Supply Current, power down I pd Input Levels MCLR , OSC1, RTCC ...
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... Parallax SX20AC/SX28AC 17.3. AC Characteristics SX20/28AC at 75 MHz(Temp Range: 0°C <= Ta <= +70°C) SX20/28AC at 50 MHz (Temp Range: -40°C <= Ta <= +85°C) Symbol Parameter External CLKIN Frequency F osc Oscillator Frequency External CLKIN Period T osc Oscillator Period Clock in (OSC1) Low or High Time osL osH Note: Data in the Typical (“ ...
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... Parallax SX20AC/SX28AC 17.5. Typical Performance Characteristics (25°C) © Parallax Inc. Page www.parallax.com Rev 1.6 11/20/2006 ...
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... Parallax SX20AC/SX28AC 17.5. Typical Performance Characteristics (25°C) Continued © Parallax Inc. Page www.parallax.com Rev 1.6 11/20/2006 ...
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... Parallax SX20AC/SX28AC 17.5. Typical Performance Characteristics (25°C) Continued © Parallax Inc. Page www.parallax.com Rev 1.6 11/20/2006 ...
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... Parallax SX20AC/SX28AC 18.0 PACKAGE DIMENSIONS 18.1. SX20AC/SS © Parallax Inc. Page www.parallax.com Rev 1.6 11/20/2006 ...
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... Parallax SX20AC/SX28AC 18.2. SX28AC/SS © Parallax Inc. Page www.parallax.com Rev 1.6 11/20/2006 ...
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... Parallax SX20AC/SX28AC 18.3. SX28AC/DP © Parallax Inc. Page www.parallax.com Rev 1.6 11/20/2006 ...
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... Parallax SX20AC/SX28AC 19.0 MANUFACTURING INFORMATION 19.1. Reflow Peak Temperature Package Type Reflow Peak Temp. Leaded Green/RoHS 19.2. MSL3 Compliance Chips shipped in production quantities are MSL3 compliant. For chips shipped in sample quantities or stored in compromised packaging, remove excess moisture before assembly by baking at 93 °C for 12 hours immediately before commencing soldering production ...
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... Parallax SX20AC/SX28AC © Parallax Inc. Page www.parallax.com Rev 1.6 11/20/2006 ...
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... Parallax SX20AC/SX28AC © Parallax Inc. Page www.parallax.com Rev 1.6 11/20/2006 ...