CY8C26443-24PVXI Cypress Semiconductor Corp, CY8C26443-24PVXI Datasheet - Page 73

• Manufacturer Part Number: CY8C26443-24PVXI
• Description: IC MCU 16K FLASH 256B 28-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ CY8C26xxxr

Specifications of CY8C26443-24PVXI

• Core Processor: M8C
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: SPI, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.25 V
• Data Converters: A/D 1x8b, 1x11b, 1x12b; D/A 1x9b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Technology: CMOS
• Processing Unit: Microcontroller
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Package Type: SSOP
• Screening Level: Industrial
• Pin Count: 28
• Mounting: Surface Mount
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 428-1643

10.4
The references in the analog array are driven by single
op-amps. A single ground referred signal is taken as the
reference input and then offset with respect to analog
ground. The reference can be input on a pin, it can be
taken from the bandgap, or it can be set to be the sup-
plies. A series of op-amps are used to do the level shift-
ing and buffering for driving the array. As more loads are
added on the reference lines, the response will slow
down. Settling time will be roughly linear with load.
A separate bias circuit controls the 3 rows. The first row
is to be controlled independently. The second and third
rows have their bias control tied together.
Table 62:
Analog Reference Control Register (ARF_CR, Address = Bank 0, 63h)
September 5, 2002
Bit 7 : BGT Bandgap Test used for internal reference voltage testing (customer should not alter; must be written as 0)
Bit 6 : HBE Bias level control for op-amps
0 = Low bias mode for analog array
1 = High bias mode for analog array
Bit [5:3] : REF [2:0] Analog Array Reference Control
0 0 0 = Vcc/2
0 0 1 = P2[4]
0 1 0 = Vcc/2
0 1 1 = 2 Bandgap ± Bandgap
1 0 0 = 2 Bandgap ± P2[6]
1 0 1 = P2[4]
1 1 0 = Reserved
1 1 1 = Reserved
Bit [2:0] : PWR [2:0] Analog Array Power Control
0 0 0 = All Analog Off
0 0 1 = SC Off, REFPWR Low
0 1 0 = SC Off, REFPWR Med
0 1 1 = SC Off, REFPWR High
1 0 0 = SC On, REFPWR Off
1 0 1 = SC On, REFPWR Low
1 1 0 = SC On, REFPWR Med
1 1 1 = SC On, REFPWR High
Read/Write
Bit Name
Bit #
POR
AGND
Analog Reference and Bias
Control
Analog Reference Control Register
High/Low
± Bandgap
± P2[6]
± Vcc/2
± Bandgap
BGT
RW
7
0
HBE
RW
6
0
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
REF[2]
RW
5
0
REF[1]
RW
4
0
10.5
BGT Bandgap Test is used for internal reference voltage
testing.
HBE controls the bias level. There is a trade-off in the
usage of this bias level. At high bias levels, the op-amp
swings are more limited but the op-amp can be faster. At
low bias levels, wider swings (and hence lower supply
voltages) are possible, but the op-amp is slower.
REF denotes Analog Array Reference Control.
PWR denotes Analog Array Power Control.
REF[0]
RW
AGND, REFHI, REFLO
3
0
PWR[2]
RW
2
0
PWR[1]
RW
1
0
Analog PSoC Blocks
PWR[0]
RW
0
0
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