MC68HC908JK3CDW Freescale Semiconductor, MC68HC908JK3CDW Datasheet - Page 159

• Manufacturer Part Number: MC68HC908JK3CDW
• Description: IC MCU 8MHZ 4K FLASH 20-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908JK3CDW

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 15
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 12x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Connectivity: -

12.6.3 Port D Control Register (PDCR)
MC68H(R)C908JL3
Freescale Semiconductor
—
Rev. 1.1
Address:
When DDRDx is a logic 1, reading address $0003 reads the PTDx data
latch. When DDRDx is a logic 0, reading address $0003 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit.
of the port D pins.
The Port D Control Register enables/disables the pull-up resistor and
slow-edge high current capability of pins PTD6 and PTD7.
SLOWDx — Slow Edge Enable
PTDPUx — Pull-up Enable
1. X = don’t care
2. Hi-Z = high impedance
3. Writing affects data register, but does not affect the input.
Reset:
Read:
Write:
DDRD
The SLOWD6 and SLOWD7 bits enable the Slow-edge, open-drain,
high current output (25mA sink) of port pins PTD6 and PTD7
respectively. DDRx bit is not affected by SLOWDx.
The PTDPU6 and PTDPU7 bits enable the 5k pull-up on PTD6 and
PTD7 respectively, regardless the status of DDRDx bit.
Bit
0
1
1 = Slow edge enabled; pin is open-drain output
0 = Slow edge disabled; pin is push-pull
1 = Enable 5k pull-up
0 = Disable 5k pull-up
$000A
Bit 7
0
0
Figure 12-12. Port D Control Register (PDCR)
PTD Bit
X
X
(1)
6
0
0
Table 12-3. Port D Pin Functions
I/O Ports
Input, Hi-Z
I/O Pin
Output
Mode
0
5
0
(2)
Table 12-3
4
0
0
Read/Write
DDRD[7:0]
DDRD[7:0]
Accesses
to DDRA
SLOWD7
3
0
summarizes the operation
SLOWD6
2
0
Read
Accesses to PTD
Pin
Pin
PTDPU7
1
0
Technical Data
PTD[7:0]
PTD[7:0]
Write
I/O Ports
PTDPU6
Bit 0
0
157
(3)