N80C196NT Intel, N80C196NT Datasheet - Page 31

• Manufacturer Part Number: N80C196NT
• Description: IC MPU 16-BIT 5V 20MHZ 68-PLCC
• Manufacturer: Intel
• Series: 80Cr

Specifications of N80C196NT

• Rohs Status: RoHS non-compliant
• Core Processor: MCS 96
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, SSIO
• Peripherals: WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-PLCC
• Eeprom Size: -
• Program Memory Size: -
• Other names: 804261

SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM MODE WITH REPEATED PROG PULSE
AND AUTO INCREMENT
This data sheet (272267-004) applies to devices
marked with a ‘‘D’’ at the end of the top side tracking
number
8XC196NT Design Considerations
1 When operating in bus timing modes 1 or 2 the
8XC196NT ERRATA see Faxback
1 ILLEGAL Opcode interrupt vector
2 Aborted Interrupt vectors to lowest priority
3 PTS Request during Interrupt latency
DATA SHEET REVISION HISTORY
This datasheet applies to devices marked with a ‘‘D’’
at the end of the topside tracking number The top-
side tracking number consists of nine characters
and is the second line on the top side of the device
Datasheets are changed as new device information
becomes available Verify with your local Intel sales
office that you have the latest version before finaliz-
ing a design or ordering devices
upper and lower address data lines must be
latched Even in 8-bit bus mode the upper ad-
dress lines must be latched In modes 0 and 3
the upper address lines DO NOT NEED to be
latched in 8-bit bus width mode But in 16-bit
buswidth mode the upper address lines need to
be latched
2344
The following are differences between the 272267-
003 and 272267-004 datasheets
1
2
3
4
5
6
7
8
9
10 T
11 T
12 T
13 T
14 Added the 8XC196NT ERRATA section
Changed all references of ‘‘EPROM’’ to
‘‘OTPROM’’
Added all the Slave Port pins to the package
diagram and pin descriptions
Added INTOUT pin to pin descriptions
Changed ILI1 (input leakage current for Port 0)
from
Removed T
waveform diagrams
T
min to
T
b
Clarified the Ready waveform timings for Mode
0 and 3 by adding ‘‘
T
to T
min to 0 5 T
min to 0 5 T
to T
were changed to reflect the minimum baudrate
for receive and transmit modes
RLCL
WHQX
LHLL
AVLL
LLAX
LHLL
XLXL
30 min to T
OSC
OSC
g
in Mode 1 changed from T
in Mode 2 changed from T
in Mode 1 changed from 0 5 T
in Mode 1 changed from 0 5 T
in Mode 0 and 3 changed from
and T
1 A to
b
in Mode 0 and 3 changed from T
b
b
5 ns min
20 min
20 min
LLYV
OSC
OSC
XLXH
OSC
g
b
b
3 A
from AC characterisics and
for the Serial Port timings
b
20 min
25 min
a
35 min
2 T
OSC
’’
OSC
OSC
8XC196NT
272267 –23
OSC
OSC
b
b
10 min
10 min
a
b
b
4 ns
OSC
15
20
31