AD8512ARZ Analog Devices Inc, AD8512ARZ Datasheet - Page 18

IC OPAMP JFET 8MHZ DUAL LN 8SOIC

AD8512ARZ

Manufacturer Part Number
AD8512ARZ
Description
IC OPAMP JFET 8MHZ DUAL LN 8SOIC
Manufacturer
Analog Devices Inc
Type
General Purpose Amplifierr
Datasheet

Specifications of AD8512ARZ

Slew Rate
20 V/µs
Design Resources
Precision, Bipolar Configuration for the AD5546/56 DAC (CN0024) Precision, Bipolar, Configuration for AD5547/AD5557 DAC (CN0028)
Amplifier Type
J-FET
Number Of Circuits
2
Gain Bandwidth Product
8MHz
Current - Input Bias
25pA
Voltage - Input Offset
100µV
Current - Supply
2.2mA
Current - Output / Channel
70mA
Voltage - Supply, Single/dual (±)
±4.5 V ~ 18 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Op Amp Type
Precision
No. Of Amplifiers
2
Bandwidth
8MHz
Supply Voltage Range
± 5V To ± 15V
Amplifier Case Style
SOIC
No. Of Pins
8
Operating Temperature Range
-40°C To +85°C
Rail/rail I/o Type
No
Number Of Elements
2
Unity Gain Bandwidth Product
8MHz
Common Mode Rejection Ratio
86dB
Input Offset Voltage
0.9@±5VmV
Input Bias Current
75pA
Single Supply Voltage (typ)
Not RequiredV
Dual Supply Voltage (typ)
±9/±12V
Voltage Gain In Db
100.59dB
Power Supply Rejection Ratio
86dB
Power Supply Requirement
Dual
Shut Down Feature
No
Single Supply Voltage (min)
Not RequiredV
Single Supply Voltage (max)
Not RequiredV
Dual Supply Voltage (min)
±5V
Dual Supply Voltage (max)
±15V
Technology
JFET
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
8
Package Type
SOIC N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Output Type
-
-3db Bandwidth
-
Lead Free Status / Rohs Status
Compliant

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Quantity
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AD8510/AD8512/AD8513
Crosstalk
Crosstalk, also known as channel separation, is a measure of
signal feedthrough from one channel to another on the same
IC. The AD8512/AD8513 have a channel separation of better
than −90 dB for frequencies up to 10 kHz and of better than
−50 dB for frequencies up to 10 MHz. Figure 57 shows the
typical channel separation behavior between Amplifier A
(driving amplifier) and each of the following: Amplifier B,
Amplifier C, and Amplifier D.
CROSSTALK = 20 log
–100
–120
–140
–160
–20
–40
–60
–80
0
100
18V p-p
V
IN
Figure 55. Pulse-Width Modulation
2
3
Figure 56. Crosstalk Test Circuit
1k
Figure 57. Channel Separation
+V
10V
V
S
8
OUT
5kΩ
IN
TIME (2ms/DIV)
1
10k
FREQUENCY (Hz)
V
OUT
7
5kΩ
20kΩ
100k
–V
CH B
CH D
4
S
6
5
1M
CH C
2.2kΩ
10M
Rev. I | Page 18 of 20
The AD8510 single has two additional active terminals that are
not present on the AD8512 dual or AD8513 quad parts. These
pins are labeled “null” and are used for fine adjustment of the
input offset voltage. Although the guaranteed maximum offset
voltage at room temperature is 400 μV and over the −40°C to
+125°C range is 800 mV maximum, this offset voltage can be
reduced by adding a potentiometer to the null pins as shown in
Figure 58. With the 20 kΩ potentiometer shown, the adjustment
range is approximately ±3.5 mV. The potentiometer parallels
low value resistors in the drain circuit of the JFET differential
input pair and allows unbalancing of the drain currents to
change the offset voltage. If offset adjustment is not required,
these pins should be left unconnected.
Caution should be used when adding adjusting potentiometers to
any op amp with this capability for several reasons. First, there is
gain from these nodes to the output; therefore, capacitive coupling
from noisy traces to these nodes will inject noise into the signal
path. Second, the temperature coefficient of the potentiometer
will not match the temperature coefficient of the internal resistors,
so the offset voltage drift with temperature will be slightly affected.
Third, this provision is for adjusting the offset voltage of the
op amp, not for adjusting the offset of the overall system. Although
it is tempting to decrease the value of the potentiometer to attain
more range, this will adversely affect the dc and ac parameters.
Instead, increase the potentiometer to 50 kΩ to decrease the
range if needed.
INPUT
+
Figure 58. Optional Offset Nulling Circuit
2
3
AD8510
1
V–
5
4
20kΩ
7
V
TYPICALLY ±3.5mV
6
OS
TRIM RANGE IS
V+
OUTPUT

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