AD600JR-REEL7 Analog Devices Inc, AD600JR-REEL7 Datasheet - Page 22

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AD600JR-REEL7

Manufacturer Part Number
AD600JR-REEL7
Description
IC AMP VGA DUAL LN 50MA 16SOIC
Manufacturer
Analog Devices Inc
Series
X-AMP®r
Datasheet

Specifications of AD600JR-REEL7

Rohs Status
RoHS non-compliant
Amplifier Type
Variable Gain
Number Of Circuits
2
Slew Rate
275 V/µs
-3db Bandwidth
35MHz
Current - Input Bias
350nA
Current - Supply
11mA
Current - Output / Channel
50mA
Voltage - Supply, Single/dual (±)
±4.75 V ~ 5.25 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
16-SOIC (0.300", 7.5mm Width)
Output Type
-
Gain Bandwidth Product
-
Voltage - Input Offset
-
AD600/AD602
A 100 dB RMS/AGC SYSTEM WITH MINIMAL GAIN
ERROR (PARALLEL GAIN WITH OFFSET)
Figure 47 shows an rms-responding AGC circuit that can be
used equally well as an accurate measurement system. It accepts
inputs of 10 μV to 1 V rms (−100 dBV to 0 dBV) with generous
overrange. Figure 48 shows the logarithmic output, V
is accurately scaled 1 V per decade, that is, 50 mV/dB, with an
intercept (V
±2 dB were introduced between the amplifiers, provided by the
±62.5 mV introduced by R6 to R9. These offsets cancel a small
gain ripple that arises in the X-AMP from its finite interpolation
error, which has a period of 18 dB in the individual VCA
sections. The gain ripple of all three amplifier sections without
this offset (in which case, the gain errors simply add) is shown
in Figure 49; it is still a remarkably low ±0.25 dB over the
108 dB range from 6 μV to 1.5 V rms. However, with the gain
offsets connected, the gain linearity remains under ±0.1 dB over
the specified 100 dB range (see Figure 50).
(SINE WAVE)
1V rms
INPUT
MAX
LOG
3.01kΩ
= 0) at 3.16 mV rms (−50 dBV). Gain offsets of
R13
C1LO
A1LO
A2LO
C2LO
GAT1
GAT2
A1HI
A2HI
2N3906
DEC
DEC
1
2
3
4
5
6
7
8
+5V
–5V
Q1
POWER SUPPLY
DECOUPLING
+
+
NETWORK
FB
FB
U1 AD600
–5V
+5V
11.3kΩ
301kΩ
R12
0.1µF
0.1µF
R14
A1
A2
REF
Figure 47. RMS Responding AGC Circuit with 100 dB Dynamic Range
16
15
14
13
12
11
10
9
+5V DEC
A1OP
VPOS
VNEG
A2OP
A2CM
C2HI
C1HI
A1CM
–5V
R15
19.6kΩ
R16
6.65kΩ
10kΩ
R6
+5V
DEC
–5V
DEC
LOG
, which
0.1µF
–2dB
–62.5mV
0.1µF
133kΩ
133kΩ
C2
127Ω
C1
R7
Rev. E | Page 22 of 28
R4
R1
1.58kΩ
R5
220pF
U3A
0dB
127Ω
R8
C3
AD713
1/4
+2dB
+62.5mV
DEC
10kΩ
–5V
R9
487Ω
Figure 48. V
R2
U3B
NC
NC
NC
200Ω
AD713
+5V
R3
1/4
1
2
3
4
5
6
7
–1
–2
–3
–4
–5
5
4
3
2
1
0
VINP
VNEG
CAVG
VLOG
BFOP
BFIN
LOG
AD636
22µF
Plotted vs. V
U4
C5
10µ
COMM
C1LO
A1LO
A2LO
C2LO
GAT1
GAT2
A1HI
A2HI
VPOS
LDLO
V
RMS
100µ
1
2
3
4
5
6
7
8
14
13
12
11
10
9
8
IN
for Figure 47’s Circuit Showing 120 dB AGC Range
+
+
INPUT SIGNAL (V rms)
NC
NC
NC
U2 AD600
+316.2mV
3.16kΩ
1m
R10
NC = NO CONNECT
A1
A2
REF
10m
R11
46.4kΩ
U3C
4.7µF
16
15
14
13
12
11
10
9
C6
AD713
+5V DEC
1/4
C1HI
A1CM
A2OP
A2CM
C2HI
A1OP
VPOS
VNEG
100m
+5V
DEC
–5V
DEC
2µF
C4
1
V
LOG
10
V
OUT

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