CA3140M Intersil, CA3140M Datasheet - Page 8

• Manufacturer Part Number: CA3140M
• Description: IC OP AMP BIMOS 4.5MHZ 8-SOIC
• Manufacturer: Intersil

Specifications of CA3140M

• Amplifier Type: General Purpose
• Number Of Circuits: 1
• Slew Rate: 9 V/µs
• Gain Bandwidth Product: 4.5MHz
• Current - Input Bias: 10pA
• Voltage - Input Offset: 5000µV
• Current - Supply: 4mA
• Current - Output / Channel: 40mA
• Voltage - Supply, Single/dual (±): 4 V ~ 36 V, ±2 V ~ 18 V
• Operating Temperature: -55°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Output Type: -
• -3db Bandwidth: -

Bandwidth and Slew Rate
For those cases where bandwidth reduction is desired, for
example, broadband noise reduction, an external capacitor
connected between Terminals 1 and 8 can reduce the open
loop -3dB bandwidth. The slew rate will, however, also be
proportionally reduced by using this additional capacitor.
Thus, a 20% reduction in bandwidth by this technique will
also reduce the slew rate by about 20%.
Figure 5 shows the typical settling time required to reach
1mV or 10mV of the final value for various levels of large
signal inputs for the voltage follower and inverting unity gain
amplifiers.
120V
-10
10
AC
-2
-4
-6
-8
8
6
4
2
0
0.1
LOAD RESISTANCE (R
LOAD CAPACITANCE (C
SUPPLY VOLTAGE: V
T
2
3
A
= 25
FIGURE 4. METHODS OF UTILIZING THE V
CA3140
o
C
FIGURE 5A. WAVEFORM
4
7
R
S
10mV
10mV
SETTLING TIME (µs)
6
L
) = 2kΩ
L
S
) = 100pF
= ±15V
8
30V
NO LOAD
1.0
R
L
10mV
1mV
10mV
1mV
FIGURE 5. SETTLING TIME vs INPUT VOLTAGE
LOAD
1mV
FOLLOWER
INVERTING
MT
MT
2
1
1mV
CA3140, CA3140A
CE(SAT)
10
SINKING CURRENT CAPABILITY OF THE CA3140 SERIES
The exceptionally fast settling time characteristics are largely
due to the high combination of high gain and wide bandwidth
of the CA3140; as shown in Figure 6.
Input Circuit Considerations
As mentioned previously, the amplifier inputs can be driven
below the Terminal 4 potential, but a series current limiting
resistor is recommended to limit the maximum input terminal
current to less than 1mA to prevent damage to the input
protection circuitry.
Moreover, some current limiting resistance should be
provided between the inverting input and the output when
1N914
D
1
4.99kΩ
200Ω
10kΩ
5kΩ
2
3
FIGURE 5B. TEST CIRCUITS
3
2
CA3140
D
1N914
2
3
2
+15V
-15V
CA3140
4
7
SETTLING POINT
V+
0.05µF
FOLLOWER
+15V
-15V
CA3140
2kΩ
INVERTING
4
7
5kΩ
4
7
6
0.1µF
0.1µF
6
R
0.1µF
0.1µF
L
6
100pF
LOAD
100pF
5.11kΩ
SIMULATED
+HV
SIMULATED
LOAD
LOAD
2kΩ
July 11, 2005
2kΩ
FN957.10