MAX815LESA+ Maxim Integrated Products, MAX815LESA+ Datasheet - Page 12

• Manufacturer Part Number: MAX815LESA+
• Description: IC SUPERVISOR MPU LP 8SOIC
• Manufacturer: Maxim Integrated Products
• Type: Simple Reset/Power-On Resetr

Specifications of MAX815LESA+

• Number Of Voltages Monitored: 1
• Output: Push-Pull, Totem Pole
• Reset: Active Low
• Reset Timeout: 140 ms Minimum
• Voltage - Threshold: 4.7V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Monitored Voltage: 1.2 V to 5.5 V
• Undervoltage Threshold: 4.65 V
• Overvoltage Threshold: 4.75 V
• Output Type: Active Low, Push-Pull
• Manual Reset: Resettable
• Watchdog: Watchdog
• Battery Backup Switching: No Backup
• Power-up Reset Delay (typ): 250 ms
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.2 V
• Supply Current (typ): 85 uA
• Maximum Power Dissipation: 471 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Power Fail Detection: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

where C
the current being drained from the capacitor (in
Amperes), and V
ference (in Volts).
Many µP-based products require manual-reset capabil-
ity, allowing the operator, a test technician, or external
logic circuitry to initiate a reset. A logic low on MR
asserts reset. Reset remains asserted while MR is low,
and for t
has an internal pullup resistor, so it can be left open if
not used. MR can be driven with TTL/CMOS-logic lev-
els or with open-drain/collector outputs.
Connect a normally open momentary switch from MR to
GND to create a manual-reset function; external
debounce circuitry is not required.
The watchdog circuit can be used to force a reset in
the MAX815 by connecting WDO to MR. If MR is driven
from long cables, or the device is used in a noisy envi-
ronment, connect a 0.1µF capacitor to ground to pro-
vide additional noise immunity.
±1% Accuracy, Low-Power, +3V and +5V
µP Supervisory Circuits
Figure 8. MAX815 Watchdog Timing
12
RESET
RESET
WDO
WDI
MR
______________________________________________________________________________________
V
V
V
V
CC
0V
CC
0V
CC
0V
CC
0V
HOLD
RS
t
WP
(200ms) after MR returns high. This input
is the capacitance (in Farads), I
LR
t
WD
is the low-line to reset threshold dif-
t
WD
Manual Reset
t
WDO
LOAD
t
WD
is
The LOW LINE, PFO, and WDO outputs will be locked to
logic low when the power supply drops below the lock-
out threshold (typically 1V below the reset threshold).
When V
sinks current, but becomes an open circuit. High-
impedance CMOS-logic inputs can drift to undeter-
mined voltages if left undriven. If a pulldown resistor is
added to the RESET pin as shown in Figure 10, any
stray charge or leakage currents will be drained to
ground, holding RESET low. Resistor value R1 is not
critical. It should be about 100kΩ—large enough not to
load RESET, and small enough to pull RESET to
ground.
Figure 9. Timing Diagram
__________Applications Information
(MAX815)
LOW LINE
(MAX814)
RESET
V
V
V
V
WDO
CC
CC
CC
CC
MR
0
0
0
CC
V
RT
∆V
falls below 1V, the RESET output no longer
LL
RESET Output Down to V
60mV
V
LLT
Low-Voltage Operation
V
RT
t
RS
Ensuring a Valid
t
MD
t
MR
t
RS
CC
= 0V