TLE4473G V53 Infineon Technologies, TLE4473G V53 Datasheet - Page 3

• Manufacturer Part Number: TLE4473G V53
• Description: IC REGULATOR LDO DUAL PDSO-12-6
• Manufacturer: Infineon Technologies

Specifications of TLE4473G V53

• Regulator Topology: Positive Fixed
• Voltage - Output: 3.3V, 5V
• Voltage - Input: 5.6 ~ 42 V
• Voltage - Dropout (typical): -, 0.3V @ 100mA
• Number Of Regulators: 2
• Current - Output: 300mA (Max), 180mA (Max)
• Current - Limit (min): 350mA, 200mA
• Operating Temperature: -40°C ~ 150°C
• Mounting Type: Surface Mount
• Package / Case: DSO-12
• Number Of Outputs: 2
• Polarity: Positive
• Input Voltage Max: 42 V
• Output Voltage: 3.3 V, 5 V
• Output Type: Fixed
• Dropout Voltage (max): 0.6 V at 100 mA
• Output Current: 300 mA, 180 mA
• Line Regulation: 20 mV
• Load Regulation: 50 mV
• Voltage Regulation Accuracy: 3 %
• Maximum Operating Temperature: + 150 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Packages: PG-DSO-12
• Regulator Type: multiple output
• Accuracy: 3.0 %2.0 %
• Max. Output Current: 300mA180mA
• Dropout Voltage: 300mV
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SP000014118; SP000557254; TLE4473G V53; TLE4473G V53TR; TLE4473GV53NT; TLE4473GV53T

Reset and Watchdog Behaviour:
The reset output RO1 is in high-state if the voltage on the delay capacitor
or equal
greater than the reset threshold
condition”), the delay capacitor
reset output RO1 is set to low.
At power-on, the charging process of
for the power-on reset delay time.
When the voltage at the delay capacitor has reached
watchdog circuit is enabled and discharges
If there is no rising edge observed at the watchdog input,
V
the current
If a watchdog pulse (rising edge at watchdog input WI) occurs during the discharge
period,
the periodical cycle starts again.
The watchdog timing is shown in
watchdog pulses corresponds to the minimum watchdog trigger time T
capacitances on pin D1 result in larger watchdog trigger time:
If the output voltage Q2 decreases below
When the voltage at this capacitor drops below
11 (RO2), i.e. the reset output is set to low-level. If the output voltage rises above the
reset threshold,
reset time, the voltage at the capacitor reaches
high again. The value of the power-on-reset time can be set within a wide range
depending of the capacitance of
Data Sheet
t
T
D on
DL1
WI,tr max
,
, where the reset output RO1 will be set to low and
=
C
C
---------------------------- -
V
D1
=
D1
DL1
I
is charged again and the reset output stays high. After
I
0.42 ms/nF
DC1
×
DC1
. The delay capacitor
V
DU1
until
C
D2
will be charged with the constant current
V
D1
×
reaches
C
D1
C
C
D1
V
V
C
D2
DU1
RT1
D1
will be discharged rapidly. If
using
Figure
C
is charged with the current
. If the output voltage drops below
and reset will be set high again.
D1
V
starts from 0 V, which leads to the equation
RT2
Equation (1)
3
C
2. The maximum duration between two
D1
, the external capacitor
with the constant current
V
V
DU2
DL2
, a reset signal is generated at pin
V
and the reset output will be set to
DU1
C
C
analogous for Q2.
and RO1 was set to high, the
D1
D1
will be discharged down to
will be charged again with
I
DC2
I
V
DC1
V
. After the power-on-
D1
D1
Rev. 1.0, 2004-07-14
for output voltages
TLE 4473 GV53
TLE 4473 GV52
has reached
C
reaches
D2
I
is discharged.
C
DD1
D1
V
WI,tr
RT1
.
is greater
V
. Higher
DL1
(“reset
V
, the
DU1
(1)
(2)
,