MCF5249VF140 Freescale Semiconductor, MCF5249VF140 Datasheet - Page 7

• Manufacturer Part Number: MCF5249VF140
• Description: IC MPU 32B 140MHZ COLDF 160-BGA
• Manufacturer: Freescale Semiconductor
• Series: MCF524xr

Specifications of MCF5249VF140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: I²C, IDE, MMC, SPI, UART/USART
• Peripherals: DMA, I²S, POR, Serial Audio, WDT
• Number Of I /o: 47
• Program Memory Type: ROMless
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 4x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 160-MAPBGA
• Embedded Interface Type: I2C, QSPI, UART
• Digital Ic Case Style: BGA
• No. Of Pins: 160
• Operating Temperature Range: 0°C To +70°C
• Frequency Typ: 140MHz
• Termination Type: SMD
• Rohs Compliant: No
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.8V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Not Compliant

1.5
This section provides a brief summary of the functional blocks in the MCF5249. For more details refer to
the MCF5249 User’s Manual .
1.5.1
The ColdFire processor Version 2 core consists of two independent, decoupled pipeline structures to
maximize performance while minimizing core size.The instruction fetch pipeline (IFP) is a two-stage
pipeline for prefetching instructions. The prefetched instruction stream is then gated into the two-stage
operand execution pipeline (OEP), which decodes the instruction, fetches the required operands, and then
executes the required function. Because the IFP and OEP pipelines are decoupled by an instruction buffer
that serves as a FIFO queue, the IFP can prefetch instructions in advance of their actual use by the OEP,
which minimizes time stalled waiting for instructions. The OEP is implemented in a two-stage pipeline
featuring a traditional RISC data path with a dual-read-ported register file feeding an arithmetic/logic unit
(ALU).
1.5.2
The MCF5249 provides four fully programmable DMA channels for quick data transfer. Single and dual
address mode is supported with the ability to program bursting and cycle stealing. Data transfer is selectable
as 8, 16, 32, or 128-bits. Packing and unpacking is supported.
MOTOROLA
MCF5249 Functional Overview
ColdFire V2 Core
DMA Controller
MCF5249 Integrated ColdFire® Microprocessor Product Brief
160MAPBGA Ball
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 1. 160 MAPBGA Ball Assignments
Number
G12
K11
F13
F12
E3
G4
H3
K3
N8
P9
E8
B8
E7
A7
L4
L8
Go to: www.freescale.com
RSTO/sdata2_bs2
SDRAM_CS2
sdata0_sdio1
cmd_sdio2
QSPI_CS1
QSPI_CS3
BUFENb2
Function
EbuOut2
SWE
sclk3
SRE
lrck3
subr
A25
sfsy
rck
gpio 53
gpio 52
gpio 51
gpio 45
gpio 49
gpio34
gpio54
gpio24
gpio22
gpo 37
gpio17
gpio11
gpio12
GPIO
gpio8
gpio7
MCF5249 Functional Overview
7