13192DSK-A0E Freescale Semiconductor, 13192DSK-A0E Datasheet - Page 11

• Manufacturer Part Number: 13192DSK-A0E
• Description: KIT DEV STARTER FOR 13191/92
• Manufacturer: Freescale Semiconductor
• Type: 802.15.4/Zigbeer

Specifications of 13192DSK-A0E

• Contents: Hardware, Software and Documentation
• Wireless Frequency: 2.4 GHz
• Interface Type: SPI
• Modulation: DSSS OQPSK
• Security: 128 bit AES
• Silicon Manufacturer: Freescale
• Silicon Core Number: MC13191, MC13192
• Kit Application Type: Communication & Networking
• Application Sub Type: Wireless Network
• Kit Contents: 13192 Developer Starter Kit
• Rohs Compliant: Yes
• For Use With/related Products: MC13191, MC13192
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6
6.1
The MC13192 has a number of operational modes that allow for low-current operation. Transition from
the Off to Idle mode occurs when RST is negated. Once in Idle, the SPI is active and is used to control the
IC. Transition to Hibernate and Doze modes is enabled via the SPI. These modes are summarized, along
with the transition times, in
Characteristics.
6.2
The host microcontroller directs the MC13192, checks its status, and reads/writes data to the device
through the 4-wire SPI port. The transceiver operates as a SPI slave device only. A transaction between
the host and the MC13192 occurs as multiple 8-bit bursts on the SPI. The SPI signals are:
A typical interconnection to a microcontroller is shown in
Freescale Semiconductor
Hibernate
1. Chip Enable (CE) - A transaction on the SPI port is framed by the active low CE input signal. A
2. SPI Clock (SPICLK) - The host drives the SPICLK input to the MC13192. Data is clocked into the
3. Master Out/Slave In (MOSI) - Incoming data from the host is presented on the MOSI input.
4. Master In/Slave Out (MISO) - The MC13192 presents data to the master on the MISO output.
Transmit
Receive
Mode
Doze
Idle
Off
Functional Description
transaction is a minimum of 3 SPI bursts and can extend to a greater number of bursts.
master or slave on the leading (rising) edge of the return-to-zero SPICLK and data out changes
state on the trailing (falling) edge of SPICLK.
MC13192 Operational Modes
Serial Peripheral Interface (SPI)
For Freescale microcontrollers, the SPI clock format is the clock phase
control bit CPHA = 0 and the clock polarity control bit CPOL = 0.
All IC functions Off, Leakage only. RST asserted. Digital outputs are tri-stated including
IRQ
Crystal Reference Oscillator Off. (SPI not functional.) IC Responds to ATTN. Data is
retained.
Crystal Reference Oscillator On but CLKO output available only if Register 7, Bit 9 = 1
for frequencies of 1 MHz or less. (SPI not functional.) Responds to ATTN and can be
programmed to enter Idle Mode through an internal timer comparator.
Crystal Reference Oscillator On with CLKO output available. SPI active.
Crystal Reference Oscillator On. Receiver On.
Crystal Reference Oscillator On. Transmitter On.
Table 7. MC13192 Mode Definitions and Transition Times
Table
7. Current drain in the various modes is listed in
MC13192 Technical Data, Rev. 3.3
Definition
NOTE
Figure
7.
Table
Functional Description
3, DC Electrical
10 - 25 ms to Idle
7 - 20 ms to Idle
(300 + 1/CLKO) µs
to Idle
144 µs from Idle
144 µs from Idle
Transition Time
To or From Idle
11