EVAL-ADF7020-1DB7 Analog Devices Inc, EVAL-ADF7020-1DB7 Datasheet
EVAL-ADF7020-1DB7
Specifications of EVAL-ADF7020-1DB7
Related parts for EVAL-ADF7020-1DB7
EVAL-ADF7020-1DB7 Summary of contents
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FEATURES Low power, low IF transceiver Frequency bands 135 MHz to 650 MHz, direct output 80 MHz to 325 MHz, divide-by-2 mode Data rates supported 0.15 kbps to 200 kbps, FSK 0.15 kbps to 64 kbps, ASK 2 ...
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ADF7020-1 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications..................................................................................... 4 Timing Characteristics ................................................................ 8 Absolute Maximum Ratings.......................................................... 10 ESD Caution................................................................................ 10 Pin Configuration and Function Descriptions........................... ...
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GENERAL DESCRIPTION The ADF7020 low power, highly integrated FSK/GFSK/ ASK/OOK/GOOK transceiver designed for operation in the low UHF and VHF bands. The ADF7020-1 uses an external VCO inductor that allows users to set the operating frequency anywhere between ...
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... ADF7020-1 SPECIFICATIONS 3.6 V, GND = All measurements are performed using the EVAL-ADF7020-1-DBX and PN9 data sequence, unless otherwise noted. Table 1. Parameter RF CHARACTERISTICS Frequency Ranges (Direct Output) Frequency Ranges (Divide-by-2 Mode) VCO Frequency Range Phase Frequency Detector Frequency TRANSMISSION PARAMETERS Data Rate ...
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Parameter RECEIVER PARAMETERS FSK/GFSK Input Sensitivity Sensitivity at 1 kbps Sensitivity at 9.6 kbps OOK Input Sensitivity Sensitivity at 1 kbps Sensitivity at 9.6 kbps 7 LNA and Mixer, Input IP3 Enhanced Linearity Mode Low Current Mode High Sensitivity Mode ...
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ADF7020-1 Parameter PHASE-LOCKED LOOP VCO Gain Phase Noise (In-Band) Normalized In-Band Phase Noise 9 Floor Phase Noise (Out-of-Band) Residual FM PLL Settling REFERENCE INPUT Crystal Reference External Oscillator Load Capacitance Crystal Start-Up Time Input Level ADC PARAMETERS INL DNL TIMING ...
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Parameter POWER SUPPLIES Voltage Supply V DD Transmit Current Consumption 433 MHz, 0 dBm/5 dBm/10 dBm Receive Current Consumption Low Current Mode High Sensitivity Mode Power-Down Mode Low Power Sleep Mode 1 Higher data rates are achievable, depending on local ...
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ADF7020-1 TIMING CHARACTERISTICS ± 10%, VGND = 25°C, unless otherwise noted. Guaranteed by design, but not production tested Table 2. Parameter Limit MIN t <10 1 ...
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DATA RATE/32 RxCLK RxDATA DATA TxCLK DATA TxDATA FETCH SAMPLE NOTES 1. TxCLK ONLY AVAILABLE IN GFSK MODE. 1/DATA RATE Figure 4. RxData/RxCLK Timing Diagram 1/DATA RATE Figure 5. TxData/TxCLK Timing Diagram Rev Page 9 of ...
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ADF7020-1 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Parameter GND DD Analog I/O Voltage to GND Digital I/O Voltage to GND Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 VCOIN VCO Input Pin. The tuning voltage on this pin determines the output frequency of the voltage controlled oscillator (VCO). The higher the tuning voltage, ...
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ADF7020-1 Pin No. Mnemonic Description 27 SREAD Serial Data Output. This pin is used to feed readback data from the ADF7020-1 to the microcontroller. The SCLK input is used to clock each readback bit (AFC, ADC readback) from the SREAD ...
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TYPICAL PERFORMANCE CHARACTERISTICS CARRIER POWER –0.28dBm ATTEN 0.00dB REF –70.00dBc/Hz 10.00 dB/ 1 1kHz FREQUENCY OFFSET Figure 7. Phase Noise Response at 315 MHz, V REF 20dBm ATTEN 30dB NORM LOG 10 dB/ FSK LgAv V1 V2 GFSK S3 FC ...
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ADF7020-1 20 9μA 15 11μ –5 –10 –15 –20 – SETTING Figure 13. PA Output Power vs. Setting CARRIER POWER ...
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FREQUENCY SYNTHESIZER REFERENCE INPUT The on-board crystal oscillator circuitry (see Figure 19) can use an inexpensive quartz crystal as the PLL reference. The oscil- lator circuit is enabled by setting R1_DB12 high enabled by default on power-up and ...
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ADF7020-1 Analog Lock Detect This N-channel, open-drain lock detect should be operated with an external pull-up resistor of 10 kΩ nominal. When a lock has been detected, this output is high with narrow low-going pulses. Voltage Regulators The ADF7020-1 contains ...
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The VCO can be recentered, depending on the required frequency of operation, by programming the VCO adjust bits R1_DB (20:21). The VCO is enabled as part of the PLL by the PLL-enable bit, R0_DB28. The VCO needs an external 22 ...
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ADF7020-1 TRANSMITTER RF OUTPUT STAGE The PA of the ADF7020-1 is based on a single-ended, controlled current, open-drain amplifier that has been designed to deliver dBm into a 50 Ω load at a maximum frequency of 650 ...
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... DIVIDER_FACTOR and INDEX_COUNTER are programmed in Bits R2_DB (15:21) and R2_DB (27:28), respectively. For further information, see the Using GFSK on the ADF7010 section in the EVAL-ADF7010EB1 Amplitude Shift Keying (ASK) Amplitude shift keying is implemented by switching the output stage between two discrete power levels. This is accomplished by toggling the DAC, which controls the output level between two 6-bit values set up in Register 2 ...
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ADF7020-1 RECEIVER SECTION RF FRONT END The ADF7020-1 is based on a fully integrated, low IF receiver architecture. The low IF architecture facilitates a very low external component count and does not suffer from power-line- induced interference problems. Figure 29 ...
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RSSI/AGC The RSSI is implemented as a successive compression log amp following the base-band channel filtering. The log amp achieves ±3 dB log linearity. It also doubles as a limiter to convert the signal-to-digital levels for the FSK demodulator. The ...
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ADF7020-1 FREQUENCY CORRELATOR IF I LIMITERS Q IF – DEV DEV DB(4:13) DB(14) Figure 31. FSK Correlator/Demodulator Block Diagram Postdemodulator Filter A second-order digital low-pass filter removes excess noise from the demodulated bit stream at the ...
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LINEAR FSK DEMODULATOR Figure 32 shows a block diagram of the linear FSK demodulator. MUX 1 ADC RSSI OUTPUT 7 LEVEL I IF LIMITER Q FREQUENCY LINEAR DISCRIMINATOR DB(6:15) Figure 32. Block Diagram of Frequency Measurement System and ASK/OOK/Linear FSK ...
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ADF7020-1 AFC Performance The improved sensitivity performance of the Rx when AFC is enabled and in the presence of frequency errors is shown in Figure 18. The maximum AFC pull-in range is ±50 kHz, which corresponds to ±58 ppm at ...
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... Figure 34 shows the ADF7020 configuration where the internal Rx/Tx switch is used with a combined LNA/PA matching network. This is the configuration used in the ADF7020-1DBX Evaluation boards. For most applications, the slight performance degradation caused by the internal Rx/Tx switch is acceptable, allowing the user to take advantage of the cost saving potential of this solution ...
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ADF7020-1 TRANSMIT PROTOCOL AND CODING CONSIDERATIONS SYNC ID PREAMBLE WORD FIELD DATA FIELD Figure 35. Typical Format of a Transmit Protocol A dc-free preamble pattern is recommended for FSK/ASK/ OOK demodulation. The recommended preamble pattern is a dc-free pattern such ...
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TO 20.1mA 14mA _XTAL T 0 3.65mA 2.0mA REG. READY WR0 WR1 Table 13. Power-Up Sequence Description Parameter Value Description/Notes Crystal starts power-up after CE is brought high. This typically ...
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ADF7020-1 15mA TO 30mA 14mA 3.65mA 2.0mA REG. WR0 WR1 XTAL + VCO READY WR2 TxDATA Figure 39. Tx Programming Sequence and Timing Diagram Rev. 0 ...
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SERIAL INTERFACE The serial interface allows the user to program the eleven 32-bit registers using a 3-wire interface (SCLK, SDATA, and SLE). It consists of a voltage level shifter, a 32-bit shift register, and 11 latches. Signals should be CMOS ...
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ADF7020-1 REGISTER 0—N REGISTER MUXOUT 8-BIT INTEGER-N TRANSMIT/ TR1 RECEIVE 0 TRANSMIT 1 RECEIVE PLE1 PLL ENABLE 0 PLL OFF 1 PLL MUXOUT REGULATOR READY (DEFAULT ...
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REGISTER 1—OSCILLATOR/FILTER REGISTER FREQUENCY VA2 VA1 OF OPERATION 0 0 850–920 0 1 860–930 1 0 870–940 1 1 880–950 VB4 VB3 FILTER IR2 IR1 BANDWIDTH 0 0 100kHz 0 1 150kHz ...
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ADF7020-1 REGISTER 2—TRANSMIT MODULATION REGISTER (ASK/OOK MODE) GFSK MOD PA BIAS CONTROL IC2 IC1 MC3 MC2 MC1 DI1 0 TxDATA 1 TxDATA PA2 PA1 PA BIAS 0 0 5μ 7μ 9μA ...
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REGISTER 2—TRANSMIT MODULATION REGISTER (FSK MODE) GFSK MOD PA BIAS CONTROL IC2 IC1 MC3 MC2 MC1 DI1 0 TxDATA 1 TxDATA PA2 PA1 PA BIAS 0 0 5μ 7μ 9μA 1 ...
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ADF7020-1 REGISTER 2—TRANSMIT MODULATION REGISTER (GFSK/GOOK MODE) GFSK MOD PA BIAS CONTROL DI1 0 TxDATA 1 TxDATA PA2 PA1 PA BIAS 5μA 7μ 9μ 11μ IC2 IC1 ...
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REGISTER 3—RECEIVER CLOCK REGISTER SEQUENCER CLOCK DIVIDE SK8 SK7 ... ... 0 0 ... 0 0 ... . . ... 1 1 ... 1 1 Notes 1. Baseband offset clock frequency (BBOS_CLK) must be greater than 1 MHz and less ...
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ADF7020-1 REGISTER 4—DEMODULATOR SET-UP REGISTER DEMOD MODE LM2 LM1 DL8 DEMOD LOCK/SYNC WORD MATCH SERIAL PORT CONTROL—FREE RUNNING SERIAL PORT CONTROL—LOCK THRESHOLD SYNC WORD DETECT—FREE RUNNING 3 0 ...
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REGISTER 5—SYNC BYTE REGISTER Notes 1. Sync byte detect is enabled by programming Bits R4_DB (25:23) to [010] or [011]. 2. This register allows a 24-bit sync byte sequence to be stored internally. If the sync byte detect mode is ...
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ADF7020-1 REGISTER 6—CORRELATOR/DEMODULATOR REGISTER Rx RESET IF FILTER DIVIDER CA1 DEMOD 0 RESET 1 CDR ML1 MIXER LINEARITY RESET 0 DEFAULT 1 HIGH RxDATA INVERT RI1 RxDATA 0 RxDATA 1 FC9 . FC6 FC5 FC4 ...
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REGISTER 7—READBACK SET-UP REGISTER RB3 READBACK 0 DISABLED 1 ENABLED Notes 1. Readback of the measured RSSI value is valid only in Rx mode. To enable readback of the battery voltage, the temperature sensor, or the voltage at the external ...
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ADF7020-1 REGISTER 8—POWER-DOWN TEST REGISTER DB15 DB14 DB13 DB12 PD7 SW1 PD7 PA (Rx MODE OFF SW1 Tx/Rx SWITCH 0 DEFAULT (ON) 1 OFF LR2 LR1 RSSI MODE X 0 RSSI OFF X 1 RSSI ...
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REGISTER 9—AGC REGISTER DIGITAL FILTER TEST IQ FI1 FILTER CURRENT 0 LOW 1 HIGH FG2 FG1 FILTER GAIN INVALID Notes 1. Default AGC_LOW_THRESHOLD = 30, default AGC_HIGH_THRESHOLD = 70. ...
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ADF7020-1 REGISTER 10—AGC 2 REGISTER I/Q PHASE ADJUST SIQ2 SELECT IQ 0 PHASE TO I CHANNEL 1 PHASE TO Q CHANNEL Notes 1. This register is not used under normal operating conditions. REGISTER 11—AFC REGISTER Notes 1. See the Internal ...
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REGISTER 12—TEST REGISTER ANALOG TEST MUX P PRESCALER 0 4/5 (DEFAULT) 1 8/9 CS1 CAL SOURCE 0 INTERNAL 1 SERIAL IF BW CAL Using the Test DAC on the ADF7020-1 to Implement Analog FM Demodulation and Measuring of SNR The ...
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ADF7020-1 REGISTER 13—OFFSET REMOVAL AND SIGNAL GAIN REGISTER TEST DAC GAIN TEST DAC OFFSET REMOVAL Notes 1. Because the linear demodulator’s output is proportional to frequency, it usually consists of an offset combined with a relatively low signal ...
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... Lead Frame Chip Scale Package [LFCSP_VQ] 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Control Mother Board Evaluation Platform 400 MHz to 435 MHz Daughter Board 135 MHz to 650 MHz Daughter Board Rev Page 0.30 ...
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ADF7020-1 NOTES Rev Page ...
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NOTES Rev Page ADF7020-1 ...
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ADF7020-1 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05669–0–12/05(0) Rev Page ...