SI4737-C-EVB Silicon Laboratories Inc, SI4737-C-EVB Datasheet - Page 7

• Manufacturer Part Number: SI4737-C-EVB
• Description: BOARD EVAL SI4737 VERSION C
• Manufacturer: Silicon Laboratories Inc
• Type: Receiverr

Specifications of SI4737-C-EVB

• Frequency: 520kHz ~ 1.71MHz, 64MHz ~ 108MHz, 162.4MHz ~ 162.55MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: SI4737
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 5. 2-Wire Control Interface Characteristics
(V
Parameter
SCLK Frequency
SCLK Low Time
SCLK High Time
SCLK Input to SDIO
(START)
SCLK Input to SDIO
(START)
SDIO Input to SCLK
SDIO Input to SCLK
SCLK input to SDIO
(STOP)
STOP to START Time
SDIO Output Fall Time
SDIO Input, SCLK Rise/Fall Time
SCLK, SDIO Capacitive Loading
Input Filter Pulse Suppression
Notes:
DD
1. When V
2. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high
4. The Si4736/37/38/39 delays SDIO by a minimum of 300 ns from the V
5. The maximum t
= 2.7 to 5.5 V, V
high) does not occur within 300 ns before the rising edge of RST.
until after the first start condition.
minimum t
violated as long as all other timing parameters are met.
IO
HD:DAT
= 0 V, SCLK and SDIO are low impedance.
IO
HD:DAT





= 1.85 to 3.6 V, T
specification.
Setup
Setup
Hold
Setup
Hold
has only to be met when f
4,5
A
= –20 to 85 °C)
Symbol
t
t
t
t
t
HD:STA
SU:DAT
HD:DAT
SU:STO
SU:STA
t
t
t
f
t
f:OUT
HIGH
t
LOW
t
BUF
t
SCL
C
f:IN
r:IN
SP
b
SCL
Test Condition
Rev. 1.0
= 400 kHz. At frequencies below 400 KHz, t
1,2,3
Si4736/37/38/39-C40
20
20
IH
+
+
threshold of SCLK to comply with the
Min
100
1.3
0.6
0.6
0.6
0.6
1.3
0.1
0.1
—
—
0
0
---------- -
1pF
---------- -
1pF
C
C
b
b
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
HD:DAT
Max
400
900
250
300
50
50
—
—
—
—
—
—
—
may be
Unit
kHz
pF
µs
µs
µs
µs
ns
ns
µs
µs
ns
ns
ns
7