ATR2731-ILQY Atmel, ATR2731-ILQY Datasheet - Page 11

• Manufacturer Part Number: ATR2731-ILQY
• Description: IC DAB ONE-CHIP FRONT END 44SSOP
• Manufacturer: Atmel

Specifications of ATR2731-ILQY

• Rf Type: DAB, Broadcast Radio
• Frequency: 70MHz ~ 260MHz
• Features: 8.5V Supply Voltage
• Package / Case: 44-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.1
7.2
7.3
4904A–DAB–03/06
Phase Comparator and Charge Pump
Switching Outputs
D/A Converters
The tri-state phase detector causes the charge pump to source or to sink current at the output
pin PD depending on the phase relation of its input signals provided by the reference and the
main divider respectively. Four different values of this current can be selected by means of the
two-wire bus bits I50 and I100. By use of this option, changes of the loop characteristics due to
the variation of the VCO gain as a function of the tuning voltage can be reduced. The
charge-pump current can be switched off using the two-wire bus bit TRI. A change in the setting
of the charge pump current becomes active when the corresponding two-wire bus transmission
is completed. As described for the setting of the scaling factor of the programmable divider, an
internal synchronization procedure ensures that such changes do not become active while the
charge pump is sourcing or sinking current at its output pin. This behavior allows a change in the
charge pump current without restricting the controlled VCO's frequency spectrum.
A high-gain amplifier (output pin: VD), which is implemented in order to construct a loop filter, as
shown in the application circuit, can be switched off by means of the two-wire bus bit OS.
An internal lock detector checks if the phase difference of the input signals of the phase detector
is smaller than approximately 250 ns in seven subsequent comparisons. If phase lock is
detected, the open collector output pin PLCK is set to H (logical value). It should be noted that
the output current of this pin must be limited by external circuitry as it is not limited internally. If
the two-wire bus bit TRI is set to H, the lock detector function is deactivated and the logical value
of the PLCK output is undefined.
Three switching outputs controlled by the two-wire bus bits SWA, SWB, and SWC can be used
for any switching task on the front-end board. The currents of these outputs are not limited inter-
nally. They have to be limited by an external circuit.
Three D/A converters, A, B, and C, offer the possibility of generating three output voltages at a
resolution of 8 bits. These voltages appear at the output pins CAO, CBO, and CCO. The con-
verters are controlled via the two-wire bus interface by means of the control bits CA0, ..., CA7,
CB0, ..., CB7 and CC0, ..., CC7, respectively, as shown in
voltages are defined as
V
V
V
where VM = 4.25V nominally. Due to the rail-to-rail outputs of these converters, almost the full
voltage range from 0V to 8.5V can be used. A common application of these converters is the
digital synthesis of control signals for the tuning of preselectors. The output pins CAO, CBO, and
CCO must be blocked externally with capacitors (100 nF) as shown in the application circuit (see
Figure 12-1 on page
CAO
CBO
CCO
=
=
=
--------- -
128
--------- -
128
--------- -
128
V
V
V
M
M
M
j = 0
j = 0
j = 0
7
7
7
CAj
CBj
CCj
20).
2
2
2
j
j
j
Table 8-1 on page
ATR2731
12. The output
11