T5760-TGS Atmel, T5760-TGS Datasheet
T5760-TGS
Specifications of T5760-TGS
Related parts for T5760-TGS
T5760-TGS Summary of contents
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... Low-cost Solution Due to High Integration Level with Minimum External Circuitry Requirements Description The T5760/T5761 is a multi-chip PLL receiver device supplied in an SO20 package. It has been especially developed for the demands of RF low-cost data transmission systems with data rates from 1 kBaud to 10 kBaud in Manchester or Bi-phase code. ...
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... Figure 2. Block Diagram CDEM SENS AVCC AGND DGND DVCC LNAREF LNA_IN LNA LNAGND T5760/T5761 2 FSK/ASK- Dem_out demodulator and data filter Rssi Limiter out RSSI IF Amp. Sensitivity- Polling circuit reduction control logic 4. Order f0 = 950 kHz/ 1 MHz FE LPF fg = 2.2 MHz Standby logic IF Loop- Amp ...
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... Test pin, during operation at GND Not connected, connect to GND Crystal oscillator XTAL connection Digital power supply Test pin, during operation at DVCC Bit clock of data stream Digital ground Selects polling or receiving mode; Low: receiving mode, High: polling mode Data output/configuration input T5760/T5761 3 ...
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... CM (motional capacitance used, an additional XTO pulling of ±30 ppm has to be added. The resulting total LO tolerance of ±120 ppm agrees with the receiving bandwidth specification of the T5760/T5761 if the T5750 has also a total LO tolerance of ±120 ppm. Figure 4. XTO Peripherals ...
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... RF input Pin LNA_IN. The input impedance of that pin is provided in the electrical parameters. The parasitic board inductances and capacitances influence the input matching. The RF receiver T5760/T5761 exhibits its highest sensitivity if the LNA is power matched. This makes the matching to an SAW filter as well antenna easier ...
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... FSK/ASK Demodulator and Data Filter T5760/T5761 6 Since different RF input networks may exhibit slightly different values for the LNA gain, the sensitivity values given in the electrical characteristics refer to a specific input matching. This matching is illustrated in Figure 33 and exhibits the best possible sensi- tivity and at the same time power matching at RF_IN ...
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... Receiving Characteristics 4561B–RKE–10/02 The T5760/T5761 is designed to operate with data coding where the DC level of the data signal is 50%. This is valid for Manchester and Bi-phase coding. If other modulation schemes are used, the DC level should always remain within the range of V and V = 66% ...
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... Polling Circuit and Control Logic Basic Clock Cycle of the Digital Circuitry T5760/T5761 8 Figure 7. Wide Band Receiving Frequency Response 0.0 -10.0 -20.0 -30.0 -40.0 -50.0 -60.0 -70.0 -80.0 -90.0 -100.0 -12.0 -9.0 -6.0 The receiver is designed to consume less than 1 mA while being sensitive to signals from a corresponding transmitter ...
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... The receiver remains in that condition until another value for Sleep is programmed into the OPMODE register. This function is desirable where several devices share a single data line and may also be used for microcontroller polling – via Pin POLLING/_ON, the receiver can be switched on and off. T5760/T5761 = 1.961 µs) Clk = 2.066 µs) Clk = 8 ´ ...
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... OFF command via Pin DATA or POLLING/_ON. Output level on Pin IC_ACTIVE => high Son OFF command Figure 9. Timing Diagram for Complete Successful Bit Check ( Number of checked Bits IC_ACTIVE Bit check Dem_out Data_out (DATA) T Start-up Start-up mode T5760/T5761 10 Sleep Sleep x 1024 x T Clk T : Clk Startup Startup T ...
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... If the calculated value for Lim_min is <19 recommended to check bits ( prevent switching to receiving mode due to noise. Bit-check T5760/T5761 is set to a higher value, the receiver is less likely to is set to a lower value. In polling mode, the bit-check . Figure 9 shows an example where 3 bits are tested ...
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... Dem_out Bit-check- 0 counter T Start-up Start-up mode T5760/T5761 12 Figure 14, Figure 15 and Figure 16 illustrate the bit check for the bit-check limits Lim_min = 14 and Lim_max = 24. When the IC is enabled, the signal processing circuits are enabled during T . The output of the ASK/FSK demodulator (Dem_out) is unde- Startup fined during that period ...
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... DATA_L_max the transmitter data stream. Figure 16 gives an example where Dem_out remains Low after the receiver has switched to receiving mode T5760/T5761 is given in the electrical Bit-check resulting in a lower current consump- Bit-check is dependent on the frequency of Bit-check ...
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... Figure 16. Steady L State Limited DATA Output Pattern After Transmission IC_ACTIVE Bit check Dem_out Data_out (DATA) Start-up mode Switching the Receiver Back to Sleep Mode T5760/T5761 14 t DATA_min t ee Receiving mode Bit-check mode After the end of a data transmission, the receiver remains active. Depending of the bit Noise_Disable in the OPMODE register, the output signal at Pin DATA is high or random noise pulses appear at Pin DATA (see chapter ’ ...
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... Bit 1 ("1") (Start bit) OFF-command t t on2 on3 X X Receiving mode Sleep mode Start-up mode t on1 Sleep mode Start-up mode T5760/T5761 T T Sleep Start-up Sleep mode Start-up mode Bit check Bit-check mode Receiving mode X X Receiving mode 15 ...
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... Data Clock Generation of the Data Clock T5760/T5761 16 Figure 18 illustrates how to set the receiver back to polling mode via Pin POLLING/_ON. The Pin POLLING/_ON must be held to low for the time period t edge on Pin POLLING/_ON and the delay t time T elapses. Sleep This command is faster than using Pin DATA at the cost of an additional connection to the microcontroller ...
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... Receiving mode, data clock control logic active Data Logical error (Manchester code violation) '1' '1' '1' '0' '1' '1' Receiving mode, data clock control logic active T5760/T5761 Data '1' '1' '0' '1' ' Delay P_Data_Clk Receiving mode, data clock control logic active OR T > Lim_min_2T Lim_max_2T ...
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... Figure 24. Timing Characteristic of the Data Clock (Rising Edge on Pin DATA) Data_Out Serial bi-directional data line Data_In DATA_CLK Figure 25. Timing Characteristic of the Data Clock (Falling Edge of the Pin DATA) Data_Out Serial bi-directional data line Data_In DATA_CLK T5760/T5761 18 Data Bit check ok '1' '1' '1' '1' '1' '0' Start bit Receiving mode, ...
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... Timing error ee Lim_min Lim_max T ee Data stream '1' '1' '1' Receiving mode, data clock control logic active T5760/T5761 Bit check ok Preburst Data Digital Noise Receiving mode, Receiving mode, data clock control bit check aktive logic active Bit check ok Preburst Data Receiving mode, ...
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... Pin POLLING/_ON must be set to High. This way of suppressing the noise is recommended if the data stream is not Manchester or Bi-phase coded. The T5760/T5761 receiver is configured via two 12-bit RAM registers called OPMODE and LIMIT. The registers can be programmed by means of the bidirectional DATA port. ...
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... USA/Europe: BR_Range2 = 3.2 kBaud to 5.6 kBaud) XLim = 2 BR_Range3 1 1 (Application USA/Europe: BR_Range3 = 5.6 kBaud to 10 kBaud) XLim = 1 Table 5. Effect of the Configuration word N N Bit-check BitChk1 BitChk0 T5760/T5761 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 – – – – Sleep Sleep X Sleep2 Sleep1 Sleep0 ...
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... T5760/T5761 22 Table 6. Effect of the Configuration Bit Modulation Modulation ASK/_FSK 0 1 Table 7. Effect of the Configuration Word Sleep Sleep Sleep4 Sleep3 Sleep2 Sleep1 ... ... ... ... ... ... ... ... Table 8. Effect of the Configuration Bit XSleep XSleep XSleep Std 0 1 Table 9. Effect of the Configuration Bit Noise Suppression Noise Suppression Noise_Disable ...
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... T5760/T5761 Lower Limit Value for Bit Check = Lim_min × XLim × Lim_min Clk (default 347 µs for f = 868.3 MHz and Lim_min RF BR_Range0 T = 329 µs for f = 915 MHz and Lim_min RF BR_Range0 Upper Limit Value for Bit Check (TLim_max = (Lim_max - 1) × XLim × ...
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... X Data_out (DATA) T5760/T5761 24 The T5760/T5761 implies an integrated power-on reset and brown-out detection circuitry to provide a mechanism to preserve the RAM register information. According to Figure 30, a power-on reset (POR) is generated if the supply voltage V drops below the threshold voltage V the configuration registers in that condition. Once V canceled after the minimum reset period t voltage of the receiver is turned on ...
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... Pin DATA for the time period t7 during t5, the according bit is set to ’0’ programming pulse t7 is issued, this bit is set to ’1’. All 15 bits are subsequently programmed this way. The time frame to program a bit is defined by t6. T5760/T5761 t9 t8 ...
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... Data Interface T5760/T5761 26 Bit 15 is followed by the equivalent time window t9. During this window, the equivalence acknowledge pulse t8 (E_Ack) occurs if the just programmed mode word is equivalent to the mode word that was already stored in that register. E_Ack should be used to verify that the mode word was correctly transferred to the register. The register must be pro- grammed twice in that case ...
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... LNA_IN TEST3 11 TEST2 10 LNAGND C16 C17 5.6p 18p ±0.1p 5% np0 np0 Toko LL1608-FS4N7S 4.7nH, ±0.3nH EPCOS B3570 5 OUT 6 OUT_GND 7 CASE_GND 8 CASE_GND T5760/T5761 IC_ACTIVE Sensitivity reduction >= 1.6k DATA POLLING/_ON DATA_CLK C12 10n 10% Q1 C11 12p 6.77617 MHz np0 2% IC_ACTIVE Sensitivity reduction >= 1.6k ...
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... Figure 11 and BR_Range2 T Startup Figure 12) BR_Range3 Time for bit Average bit-check check (see time while polling, Figure 11 applied (see Figure 15 and Figure 16) T Bit-check BR_Range0 BR_Range1 BR_Range2 BR_Range3 T5760/T5761 28 Symbol tot stg T amb P in_max Symbol R thJA = -40°C to +105° amb ...
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... T5760/T5761 = 868.3 MHz and 915 MHz Variable Oscillator Typ. Max. Min. Typ. 1 ´ T XClk 3.5/f 3/f Sig Sig 6.5/f 6/f Sig Sig 9 ...
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... BR_Range0 edge at DATA BR_Range1 t Delay2 and BR_Range2 DATA_CLK BR_Range3 Pulse width of BR_Range = negative pulse BR_Range0 at Pin BR_Range1 t P_DATA_CLK DATA_CLK BR_Range2 BR_Range3 T5760/T5761 30 = -40°C to +105° amb 25°C) S amb f = 868.3 MHz 6.77617 MHz Oscillator 7.14063 MHz Oscillator Min. Typ. Max. ...
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... ASK (level of carrier) BER £ 100% Mod f = 868.3 MHz/915 MHz ° amb f = 950 kHz/1 MHz IF BR_Range0 BR_Range1 BR_Range2 BR_Range3 T5760/T5761 = 868.3 MHz and f 0 Symbol Min. Typ. IS 170 off IS on 7.8 7.4 IIP3 -16 IS -70 LORF NF 5 200 || 3.2 ...
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... S/N ratio to suppress inband noise signals. Noise signals may have any modulation scheme Dynamic range RSSI amplifier Lower cut-off frequency of the data filter Recommended CDEM for best performance T5760/T5761 32 = -40°C to +105° amb 25°C) S amb Test Conditions f = 868.3 MHz/915 MHz ...
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... Sense = 120 Sense = 150 Sense + Red Ref_Red Red £ 0 IDATA_CLK = 1mA IDATA_CLK = -1mA IIC_ACTIVE = 1 mA IIC_ACTIVE = -1 mA T5760/T5761 = 868.3 MHz and f 0 Symbol Min. Typ. 270 156 t ee_sig 89 50 2.8 3.4 fu 4.8 6.0 8.0 10.0 15.0 19.0 P -63 -68 Ref_Red P -72 -77 Ref_Red ...
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... V Parameters POLLING/_ON input - Low level input voltage - High level input voltage TEST 4 pin - High level input voltage TEST 1 pin - Low level input voltage Ordering Information Extended Type Number T5760-TGS T5760-TGQ T5761-TGS T5761-TGQ Package Information Package SO20 Dimensions in mm 0.4 1. ...
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