U3741BM-P2FL Atmel, U3741BM-P2FL Datasheet
U3741BM-P2FL
Specifications of U3741BM-P2FL
Related parts for U3741BM-P2FL
U3741BM-P2FL Summary of contents
Page 1
... Different IF Bandwidth Versions are Available (300 kHz and 600 kHz) Description The U3741BM is a multi-chip PLL receiver device supplied in an SO20 package. It has been specially developed for the demands of RF low-cost data transmission systems with low data rates from 1 kBaud to 10 kBaud (1 kBaud to 3.2 kBaud for FSK) in Manchester or Bi-phase code ...
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... Remote control transmitter 1 Li cell U2741B Encoder ATARx9x Keys Block Diagram FSK/ASK CDEM AVCC SENS AGND DGND MIXVCC LNAGND LNA_IN U3741BM 2 UHF ASK/FSK U3741BM PLL Antenna Antenna XTO VCO Power amp. FSK/ASK- DEMOD_OUT Demodulator and data filter RSSI Limiter out Sensitivity IF Amp reduction th 4 ...
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... Low: polling mode off (sleep mode) H: polling mode on (active mode) 20 DATA Data output/configuration input 4662B–RKE–10/04 Figure 1. Pinning SO20 SENS FSK/ASK CDEM AVCC AGND DGND MIXVCC LNAGND LNA_IN NC U3741BM 1 20 DATA 2 19 ENABLE 3 18 TEST 4 17 POUT 5 16 MODE 6 15 ...
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... RF Front End U3741BM 4 The RF front end of the receiver is a heterodyne configuration that converts the input signal into a 1-MHz IF signal. According to the block diagram, the front end consists of an LNA (low noise amplifier), LO (local oscillator), a mixer and RF amplifier. The LO generates the carrier frequency for the mixer via a PLL synthesizer. The XTO ...
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... LNA_IN. The input impedance of that pin is provided in the electrical parame- ters. The parasitic board inductances and capacitances also influence the input matching. The RF receiver U3741BM exhibits its highest sensitivity at the best sig- nal-to-noise ratio in the LNA. Hence, noise matching is the best choice for designing the transformation network ...
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... C3 L LNA_IN 25n 47p C16 100p 315 MHz 47n RF L2 TOKO LL2012 RF F82NJ IN 1 B3551 IN 82n 2 C2 IN_GND CASE_GND 10p LNAGND U3741BM 9 LNA_IN 33p 25n 3.3p 100p 39n TOKO LL2012 F39NJ C17 22p TOKO LL2012 F47NJ 5 OUT 6 OUT_GND 4662B–RKE–10/04 ...
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... VS or GND via a microcontroller or by the digital output port Sense POUT of the U3741BM receiver IC. The receiver can be switched from full sensitivity to reduced sensitivity or vice versa at any time. In polling mode, the receiver will not wake up if the RF input signal does not exceed the selected sensitivity. If the receiver is already active, the data stream at pin DATA will disappear when the input signal is lower than defined by the reduced sensitivity ...
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... Receiver” on page 17). BR_Range must be set in accordance to the used baud rate. The U3741BM is designed to operate with data coding where the DC level of the data signal is 50%. This is valid for Manchester and Bi-phase coding. If other modulation schemes are used, the DC level should always remain within the range of VDC_min = 33% and VDC_max = 66% ...
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... Receiving Characteristics 4662B–RKE–10/04 The RF receiver U3741BM can be operated with and without a SAW front-end filter typical automotive application, a SAW filter is used to achieve better selectivity. The selectivity with and without a SAW front end-filter is illustrated in Figure 6. This example relates to ASK mode and the 300-kHz bandwidth version of the U3741BM. FSK mode and the 600-kHz version of the receiver exhibit similar behavior ...
Page 10
... Polling Circuit and Control Logic Basic Clock Cycle of the Digital Circuitry U3741BM 10 The receiver is designed to consume less than 1 mA while being sensitive to signals from a corresponding transmitter. This is achieved via the polling circuit. This circuit enables the signal path periodically for a short time. During this time the bit check logic verifies the presence of a valid transmitter signal ...
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... T XClk Clk XClk Clk = I S Soff = I . The average current consumption in S Son + T Bitcheck and the startup time of a connected microcontroller + T Start_ C is about Sleep can be set bit X Sleep Sleep U3741BM is defined XClk . During the start-up Startup ) to Bitcheck is Sleep or by SleepStd 11 ...
Page 12
... It can be set to Sleep mode through an OFF command via pin DATA or ENABLE SON U3741BM implies the standard extension factor. The sleep time is always extended. SleepStd implies the temporary extension factor. The extended sleep time is used SleepTemp as long as every bit check is OK ...
Page 13
... In polling mode, the bit Bitcheck . Figure 9 shows an example where 3 bits are Bitcheck is in between the lower bit check limit the check will be continued the bit check will be terminated and the receiver 1/f Sig lim_min T lim_max U3741BM and Lim_min is smaller than ee and Lim_min . Using ee 13 ...
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... Bit check 0 Counter Figure 12. Timing Diagram for Failed Bit Check (Condition: CV_Lim < Lim_min) (Lim_min = 14, Lim_max = 24) Enable IC Bit check Dem_out Bit check 0 Counter Startup Mode U3741BM 14 The bit check limits are determined by means of the formula below Lim_min T Lim_min XClk T = (Lim_max –1) T Lim_max XClk Lim_min and Lim_max are defined by a 5-bit word each within the LIMIT register ...
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... Bitcheck Bitcheck . This clock is also used for XClk XClk is to some extent affected by the pre- DATA_min as illustrated in Figure 15 DATA_min DATA_L_max U3741BM Bitcheck . A higher Clk Bitcheck , the receiver elapsed. The is in between the = tmin2 is the . This function 15 ...
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... Lim_min t ee Figure 16. Steady L State Limited DATA Output Pattern after Transmission Enable IC Bit check Dem_out DATA Sleep mode Switching the Receiver Back to Sleep Mode U3741BM CV_Lim < Lim_max tmin1 CV_Lim < Lim_min or CV_Lim t ee Bit check mode Receiving mode After the end of a data transmission, the receiver remains active and random noise pulses appear at pin DATA ...
Page 17
... Doze Sleep toff The U3741BM receiver is configured via two 12-bit RAM registers called OPMODE and LIMIT. The registers can be programmed by means of the bi-directional DATA port. If the register contents have changed due to a voltage drop, this condition is indicated by a certain output pattern called reset marker (RM). The receiver must be reprogrammed in that case ...
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... Table 4. Effect of the Configuration Word BR_Range BR_Range Baud1 Baud0 U3741BM 18 Table 2. Effect of Bit 1 and Bit 2 in Programming the Registers Bit 1 Bit 2 Action 1 x The receiver is set back to polling mode (OFF command The OPMODE register is programmed 0 0 The LIMIT register is programmed Table 4 and the following illustrate the effect of the individual configuration words ...
Page 19
... Level of the Multi-purpose Output Port POUT 0 (Default Sleep X Sleep Sleep 2ms for US-/European applications) Sleep 22.96 ms, Europe 23.31 ms) (Default) Sleep . . . (Permanent sleep mode) = Sleep Sleep 1 (Default reset bit check fails once) Sleep set permanently) Sleep set permanently) Sleep U3741BM 1024 T ) Clk X 1024 T ) Sleep Clk 19 ...
Page 20
... The U3741BM has an integrated power-on reset and brown-out detection circuitry to provide a mechanism to preserve the RAM register information. According to Figure 19 on page 21, a power-on reset (POR) is generated if the supply voltage V drops below the threshold voltage V S grammed into the configuration registers in that condition. Once V the POR is canceled after the minimum reset period t the supply voltage of the receiver is turned on ...
Page 21
... Bit 2 ("0") ("1") (Start bit) (Register select) Programming Frame The configuration registers are programmed serially via the bi-directional data line according to Figure 20 and Figure 21. Figure 21. One-wire Connection to a Microcontroller U3741BM Internal pull-up resistor DATA (U3741BM) U3741BM 1 Sleep t8 Bit 13 Bit 14 ("1") ("0") ...
Page 22
... U3741BM 22 To start programming, the serial data line DATA is pulled to ‘L’ for the time period t1 by the microcontroller. When DATA has been released, the receiver becomes the master device. When the programming delay period t2 has elapsed, it emits 14 subsequent synchronization pulses with the pulse length t3. After each of these pulses, a program- ming window occurs ...
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... Sig Sig 6.5/f Sig Sig 9.5/f Sig Sig U3741BM Unit V mW °C °C °C dBm Unit K/W Max. Unit /10) µs /14) µs T µs Clk T µs Clk T µs ...
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... BR_Range0 BR_Range1 Programming start pulse BR_Range2 (Figure 17, Figure 20) BR_Range3 after POR Programming delay period (Figure 17, Figure 20) Synchroni- zation pulse (Figure 17, Figure 20) U3741BM 6.76438-Mhz Osc. (Mode 1) Min. Typ. Max. Min 1.0 1.0 1.8 1.0 1.8 3.2 1.8 3 ...
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... MHz, unless otherwise specified. 0 Symbol Min. Typ. IS 190 off IS 7.0 on IIP3 -28 IS -73 LORF NF 7 1.0 || 1.56 Zi LNA_IN 1.3 || 1.0 IP -40 1db U3741BM Max. Unit T µs Clk T µs Clk T µs Clk 256 µs T Clk T µs Clk T µs Clk T µs Clk Max. ...
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... Analog Signal Processing Input sensitivity ASK 300-kHz IF filter Input sensitivity ASK 300-kHz IF filter Input sensitivity ASK 300-kHz IF filter Input sensitivity ASK 300-kHz IF filter Input sensitivity ASK 300-kHz IF filter Input sensitivity ASK 600 kHz IF filter U3741BM 433.92 MHz and Test Conditions ...
Page 27
... Ref_FSK Ref The sensitivity of the receiver is higher for higher values of f FSK BR_Range0 BR_Range1 BR_Range2 and BR_Range3 are not suitable for FSK operation ASK mode FSK mode U3741BM = 315 MHz, unless otherwise specified. 0 Symbol Min. Typ. Max. -108 -110 -112 -106.5 -108 ...
Page 28
... Upper cut-off frequency data filter Minimum edge-to-edge time period of the input data signal for full sensitivity Reduced sensitivity Reduced sensitivity Reduced sensitivity Reduced sensitivity Reduced sensitivity Reduced sensitivity variation over full operating range U3741BM 433.92 MHz and Test Conditions ----------------------------------------------------------- ...
Page 29
... ext POUT POUT FSK selected ASK selected Idle mode Active mode Division factor = 10 Division factor = 14 Test input must always be set to LOW U3741BM = 315 MHz, unless otherwise specified. 0 Symbol Min. Typ. Max. 0 -3.5 P Red -6.0 -9.0 -11.0 -13.5 V 1.95 2 ...
Page 30
... Ordering Information Extended Type Number U3741BM-P2FL U3741BM-P2FLG3 U3741BM-P3FL U3741BM-P3FLG3 Package Information Package SO20 Dimensions in mm 0.4 1. U3741BM 30 Package Remarks SO20 2: IF bandwidth of 300 kHz, tube SO20 2: IF bandwidth of 300 kHz, taped and reeled SO20 3: IF bandwidth of 600 kHz, tube SO20 3: IF bandwidth of 600 kHz, taped and reeled 12 ...
Page 31
... Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. 1. Put datasheet in a new template. 2. Heading rows at Table “Absolute Maximum Ratings” added. 3. Table “Ordering Information” on page 30 changed. U3741BM 31 ...
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