SI4703-B17-GMR Silicon Laboratories Inc, SI4703-B17-GMR Datasheet - Page 16

• Manufacturer Part Number: SI4703-B17-GMR
• Description: IC TUNER FM RADIO RDS/RBDS 20QFN
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4703-B17-GMR

• Frequency: 76MHz ~ 108MHz
• Sensitivity: *
• Data Rate - Maximum: *
• Modulation Or Protocol: *
• Applications: *
• Current - Receiving: *
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Features: *
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: *
• Package / Case: 20-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -

Si4703-B17
The STC bit is set after the seek operation completes.
The channel is valid if the seek operation completes and
the SF/BL bit is set low. At other times, such as before a
seek operation or after a seek completes and the SF/BL
bit is set high, the channel is valid if the AFC Rail
(AFCRL) bit is set low and the value of RSSI[7:0] is
greater than or equal to SEEKTH[7:0]. Note that if a
valid channel is found but the AFCRL bit is set, the
audio output is muted as in the softmute case discussed
in Section “4.5. Stereo Audio Processing”. The SEEK bit
must be set low after the STC bit is set high in order to
complete the seek operation. Setting the STC bit high
clears STC status and SF/BL bits. The seek operation
may be aborted by setting the SEEK bit low at any time.
The device can be configured to generate an interrupt
on GPIO2 when a tune or seek operation completes.
Setting the seek/tune complete (STCIEN) bit and
GPIO2[1:0] = 01 will configure GPIO2 for a 5 ms low
interrupt when the STC bit is set by the device.
For additional recommendations on optimizing the seek
function,
Adjustability and Settings."
4.7. Reference Clock
The Si4703 accepts a 32.768 kHz reference clock to the
RCLK pin. The reference clock is required whenever the
ENABLE bit is set high. Refer to Table 3, “DC
Characteristics,” on page 5 for switching voltage levels
and Table 7, "FM Receiver Characteristics," on page 10
for frequency tolerance information.
An onboard crystal oscillator is available to generate the
32.768 kHz reference when an external crystal and load
capacitors are provided. Refer to 2. "Typical Application
Schematic" on page 12. The oscillator must be enabled
or disabled while in powerdown (ENABLE = 0) as shown
in Figure 9, “Initialization Sequence,” on page 18.
Register 07h, bits [13:0], must be preserved as 0x0100
while in powerdown.
4.7.1. Si4703 Internal Crystal Oscillator Errata
The Si4703-B17 seek/tune performance may be
affected by data activity on the SDIO bus when using
the integrated internal oscillator. SDIO activity results
from polling the tuner for status or communicating with
other devices that share the SDIO bus. If there is SDIO
bus activity while the Si4703-B17 is performing the
seek/tune function, the crystal oscillator may experience
jitter, which may result in mistunes and/or false stops.
SDIO activity during all other operational states does
not affect performance.
For
recommends that all SDIO data traffic be suspended
during Si4703-B17 seek and tune operations. This is
16
best seek/tune
consult
"AN284:
results,
Si4700/01/02/03
Silicon
Laboratories
Confidential Rev. 1.0
Seek
achieved by keeping the bus quiet for all other devices
on the bus, and delaying tuner polling until the tune or
seek operation is complete. The STC (seek/tune
complete) interrupt should be used instead of polling to
determine when a seek/tune operation is complete.
Please refer to the Si4703-B17 data sheet for specified
seek/tune times and register use guidelines.
The layout guidelines in Si4700/01/02/03 Evaluation
Board User’s Guide, Section 8.3 Si4703 Daughter Card
should be followed to help ensure robust FM
performance.
Please refer to the posted Si4702/03 Internal Crystal
Oscillator Errata for more information.
4.8. Control Interface
Two-wire slave-transceiver and three-wire interfaces
are provided for the controller IC to read and write the
control registers. Refer to “4.9. Reset, Powerup, and
Powerdown” for a description of bus mode selection.
Registers may be written and read when the V
is applied regardless of the state of the V
supplies. RCLK is not required for proper register
operation.
4.8.1. 3-Wire Control Interface
For three-wire operation, a transfer begins when the
SEN pin is set low on a rising SCLK edge. The control
word is latched internally on rising SCLK edges and is
nine bits in length, comprised of a four bit chip address
A7:A4 = 0110b, a read/write bit (write = 0 and read = 1),
and a four bit register address, A3:A0. The ordering of
the control word is A7:A5, R/W, A4:A0. Refer to Section
5. "Register Summary" on page 19 for a list of all
registers and their addresses.
For write operations, the serial control word is followed
by a 16-bit data word and is latched internally on rising
SCLK edges.
For read operations, a bus turn-around of half a cycle is
followed by a 16-bit data word shifted out on rising
SCLK edges and is clocked into the system controller
on falling SCLK edges. The transfer ends on the rising
SCLK edge after SEN is set high. Note that 26 SCLK
cycles are required for a transfer, however, SCLK may
run continuously.
For details on timing specifications and diagrams, refer
to Table 5, “3-Wire Control Interface Characteristics,” on
page 7, Figure 3, “3-Wire Control Interface Write Timing
Parameters,” on page 7, and Figure 4, “3-Wire Control
Interface Read Timing Parameters,” on page 7.
IO
D
supply
or V
A