T48C862M-R4-TNQ Atmel, T48C862M-R4-TNQ Datasheet - Page 92

• Manufacturer Part Number: T48C862M-R4-TNQ
• Description: IC MON TIRE PRESS 433MHZ 24-SOIC
• Manufacturer: Atmel

Specifications of T48C862M-R4-TNQ

• Frequency: 433MHz
• Modulation Or Protocol: FM, FSK
• Data Rate - Maximum: 32 kBaud
• Power - Output: 10dBm
• Current - Transmitting: 9.5mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Memory Size: 1KB EEPROM, 1KB RAM
• Voltage - Supply: 2 V ~ 4 V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 24-SOIC (0.200", 5.30mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Applications: -

Write Control Bytes
Read Operations
Read One Data Byte
Read Two Data Bytes
Read n Data Bytes
92
T48C862-R4 [Preliminary]
A -> acknowledge; HB: high byte; LB: low byte; R: row address
The EEPROM allows byte-, word- and current address read operations. The read oper-
ations are initiated in the same way as write operations. Every read access is initiated by
sending the START condition followed by the control byte which contains the address
and the read mode. When the device has received a read command, it returns an
acknowledge, loads the addressed word into the read/write buffer and sends the
selected data byte to the master. The master has to acknowledge the received byte if it
wants to proceed the read operation. If two bytes are read out from the buffer the device
increments respectively decrements the word address automatically and loads the
buffer with the next word. The read mode bits determines if the low or high byte is read
first from the buffer and if the word address is incremented or decremented for the next
read access. If the memory address limit is reached, the data word address will roll over
and the sequential read will continue. The master can terminate the read operation after
every byte by not responding with an acknowledge (N) and by issuing a stop condition.
Write low byte first
Byte order
Write high byte first
Byte order
Start
Start
Start
Control byte
Control byte
Control byte
A
A
A
Data byte 1
Data byte 1
Data byte 1
A4
A4
HB(R)
LB(R)
MSB
MSB
A3
A3
Row address
Row address
A
N
A
A2
A2
Data byte 2
HB(R)
LB(R)
Data byte 2
Stop
A1
A1
A0
A0
A
N
–
C1
C1
Stop
0
1
Data byte n
C0
C0
1
0
4551C–4BMCU–01/04
R/NW
R/NW
LSB
LSB
0
0
N Stop