XRT75R03IVTR Exar Corporation, XRT75R03IVTR Datasheet - Page 24

• Manufacturer Part Number: XRT75R03IVTR
• Description: IC LIU E3/DS3/STS-1 3CH 128LQFP
• Manufacturer: Exar Corporation

Specifications of XRT75R03IVTR

• Lead Free Status / RoHS Status: Contains lead / RoHS Compliant

JITTER ATTENUATOR INTERFACE
XRT75R03
REV. 1.0.8
Microprocessor Serial INTERFACE - (HOST MODE)
P
42
43
69
68
IN
#
SDO/RxMON
S
IGNAL
SDI/RxON
JATx/Rx
JA1
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
N
AME
T
I/O
YPE
I
I
I
Jitter Attenuator Select 1:
Please see the Description above for JA0
Jitter Attenuator in Transmit/Receive Path Select Input:
This input pin is used to configure the Jitter Attenuator to operate in either the
Transmit or Receive path within each of the three (3) channels of the
XRT75R03.
"Low" - Configures the Jitter Attenuator within each channel to operate in the
Receive Path.
"High" - Configures the Jitter Attenuator within each channel to operate in the
Transmit Path.
N
Microprocessor Serial Interface - Serial Data Output:
This pin serially outputs the contents of a specified on-chip Command Register
during READ Operations via the Microprocessor Serial Interface. The data
which is output via this pin is updated upon the falling edge of the SCLK clock
signal.
This output pin will be tri-stated upon completion of a given READ operation.
N
Microprocessor Serial Interface - Serial Data Input:
This input pin functions as the Serial Data Input pin for the Microprocessor
Serial Interface. In particular, this input pin will accept all of the following data in
a serial manner during READ and WRITE operations with the Microprocessor
Serial Interface.
•
•
•
All data that is applied to this input will be sampled upon the rising edge of the
SCLK input clock signal.
N
OTES
OTE
OTE
The READ/WRITE indicator bit.
The Address Value of the Targeted Command Register for this particular
READ or WRITE operation.
The Data to be written into the targeted Command Register for a given
WRITE operation.
1. The setting of this input pin applies globally to all three (3) channels of
2. This input pin is ignored and should be tied to GND if the XRT75R03 is
: This pin functions as the RxMON input pin if the XRT75R03 has been
: This input pin will function as the RxON input pin if the XRT75R03 has
:
configured to operate in the Hardware Mode.
been configured to operate in the Hardware Mode.
the XRT75R03.
configured to operate in the Host Mode or if the Jitter Attenuators are
disabled.
21
D
ESCRIPTION
xr
xr
xr
xr