73M1903C-IM/F Maxim Integrated Products, 73M1903C-IM/F Datasheet
73M1903C-IM/F
Specifications of 73M1903C-IM/F
Related parts for 73M1903C-IM/F
73M1903C-IM/F Summary of contents
Page 1
... This interface can be configured as a single master/slave mode daisy chain mode that allows the user to connect up to eight 73M1903C devices to a single host for multi Analog Front End applications, such as, central server modems. ...
Page 2
... Analog Specifications ................................................................................................................... 33 9.1 DC Specifications .................................................................................................................... 33 9.2 AC Specifications .................................................................................................................... 33 9.3 Performance ............................................................................................................................ 34 9.3.1 Receiver ....................................................................................................................... 34 9.3.2 Transmitter ................................................................................................................... 35 10 Mechanical Drawings .................................................................................................................... 37 11 Ordering Information..................................................................................................................... 38 Appendix A .......................................................................................................................................... 39 73M1903C DAA Resistor Calculation Guide .................................................................................... 39 Trans-Hybrid Loss (THL) ................................................................................................................. 41 Appendix B .......................................................................................................................................... 42 Crystal Oscillator ............................................................................................................................. 42 PLL 43 Examples of NCO Settings .............................................................................................................. 44 Example 1 ............................................................................................................................... 44 Example 2 ............................................................................................................................... 45 Example 3 ............................................................................................................................... 46 Example 4 ...
Page 3
... Figure 2: Control Frame Position versus SPOS ........................................................................................ 8 Figure 3: Serial Port Timing Diagrams ..................................................................................................... 9 Figure 4: 73M1903C Host Connection in Master and Slave Modes ........................................................ 10 Figure 5: 73M1903C Daisy Chaining for Master/Slave Mode and Slave Modes ...................................... 10 Figure 6: Clock Generation .................................................................................................................... 19 Figure 7: Analog Block Diagram ............................................................................................................. 22 Figure 8: Overall TX Path Frequency Response at 8 kHz Sample Rate .................................................. 23 Figure 9: Frequency Response of TX Path for kHz in Band Signal at 8 kHz Sample Rate ...
Page 4
... Data Sheet 1 Pin Description The 73M1903C modem Analog Front End (AFE available in a 32-pin QFN package. VND VPD GPIO0 GPIO1 GPIO2 GPIO3 FS SCLK Table 1 describes the function of each pin. There are three pairs of power supply pins, VPA (analog), VPD (digital) and VPPLL (PLL). They should be separately decoupled from the supply source in order to isolate digital noise from the analog circuits internal to the chip ...
Page 5
... Type of frame sync late (mode0 early (mode1). Weak-pulled high – default Controls the SCLK behavior after FS. Open, weak-pulled high = SCLK Continuous; tied low = 32 clocks per R/W cycle. Delayed frame sync to support daisy chain mode with additional 73M1903C devices. 73M1903C Data Sheet 5 ...
Page 6
... Power saving is accomplished by disabling the analog front end by clearing ENFE bit (bit 7 Register00). During the normal operation, a data frame sync signal (FS) is generated by the 73M1903C at the rate of Fs. For every data FS there are 16 bits transmitted and 16 bits received. The frame synchronization (FS) signal is pin programmable for type late determined by the state of the TYPE input pin ...
Page 7
... If SPOS is set the control frame is ¼ of the way between consecutive data frames, i.e., the control frame is closer to the first data frame. This is illustrated in Figure 2. The 73M1903C IC includes a feature that shuts off the serial clock (SCLK) after 32 cycles of SCLK following the frame synch (Figure 1). The SckMode pin controls this mode. If this pin is left open, the clock will run continuously ...
Page 8
... Data Sheet 32 Cycles of SCLK SCLK FS ( early mode) 32 Cycles of SCLK SCLK FS ( late mode) Figure 1: Effect of the TYPE (FS mode with SckMode=0 DATA FRAMES CONTROL FRAMES Figure 2: Control Frame Position versus SPOS 8 SCLK Relative to early FS SCLK Relative to late FS SPOS = 0 SPOS = 1 DS_1903C_033 Rev. 5.0 ...
Page 9
... Control Frame Relation Between the Data and Control Frames (Master Mode, continuous clock, default SPOS) 73M1903C Data Sheet TX5 TX4 TX3 TX2 TX1 CTL RX5 RX4 RX3 RX2 RX1 RX0 TX5 TX4 TX3 TX2 TX1 CTL RX5 RX4 RX3 ...
Page 10
... In this mode of operation the serial clock (SCLK) and FS are inputs to 79M1903C provided by the Master device. The serial clock input must be connected to OSCIN pin while SCLK pin of 73M1903C is unconnected, except for the resistor connected to ground (see Figures 4 and 5). The 73M1903C PLL must be programmed to multiply the serial clock frequency by an appropriate factor in order to obtain Fsys ...
Page 11
... DS_1903C_033 Up to eight 73M1903C devices may be daisy-chained if the control frame sync is placed at the middle of the data frame sync interval. Four devices may be daisy-chained if the control frame sync is placed at the 1/4 of the data frame sync interval. In all cases involving slave and daisy chain operation, only hardware controlled Control Frames are supported ...
Page 12
... Data Sheet 2.3 Control Register Map Table 2 shows the map of addressable registers in the 73M1903C. Each register and its bits are described in detail in the following sections. Register Address Default Name CTRL 00h 08h TEST 01h 00h DATA 02h FFh DIR 03h ...
Page 13
... Rx Gain Selection Receive Gain RXGAIN (0X00[0 RxGain Enable. This gain selection can be used for line snoop or Caller ID detection Increase the gain of the receiver Normal operation Rev. 5.0 Bit 4 Bit 3 Bit 2 TXBST0 TXDIS RXG1 73M1903C Data Sheet Bit 1 Bit 0 RXG0 RXGAIN 13 ...
Page 14
... Bit 7 Bit 6 Bit 5 Rev(3:0) Rev(3:0) (0X06[7:4]) Contain the revision ID of the 73M1903C device. The rest of this register is for chip development purposes only and is not intended for customer use. Do not write to reserved locations. FSDEn (0X06[3]) Delayed Frame Sync Enable. This bit shall be enabled if the daisy chain mode is used ...
Page 15
... DS_1903C_033 4 GPIO Registers The 73M1903C provides 8 user definable I/O pins. Each pin is programmed separately as either an input or an output by a bit in a direction register. If the bit in the direction register is set high, the corresponding pin is an input whose value is read from the GPIO data register low, the pin will be treated as an output whose value is set by the GPIO data register ...
Page 16
... Data Sheet 5 PLL Configuration Registers Register08 (PLL_PSEQ): Address 08h Reset State 00h Bit 7 Bit 6 Bit 5 Pseq(7:0) (0X08[7:0]) This corresponds to the sequence of divisor. If Prst(2:0) setting in Register09 is 00, this register is ignored. Register09 (PLL_RST): Address 09h Reset State 0Ah Bit 7 Bit 6 Bit 5 Prst(2:0) Prst(2:0) represents the rate at which the sequence register is reset ...
Page 17
... Represents the rate at which the NCO sequence register is reset. The address 0Dh must be the last register to be written to when effecting a change in PLL. Rev. 5.0 Bit 4 Bit 3 Bit 2 Ndvsr(6:0) Bit 4 Bit 3 Bit 2 Nseq(7:0) Bit 4 Bit 3 Bit 2 – 73M1903C Data Sheet Bit 1 Bit 0 Bit 1 Bit 0 Bit 1 Bit 0 Nrst(2:0) 17 ...
Page 18
... Data Sheet Register0E (PLL_LOCK): Address 0Eh Reset State 00h Bit 7 Bit 6 Bit 5 Frcvco PwdnPLL LockDet Frcvco (0X0E[7]) Force Vco as System clock Enable Xtal oscillator as system clock forces VCO as system clock. This bit is set to 0 upon reset, PwdnPll = 1 or ENFE = 0. Both PwdnPll and ENFE are delayed coming out of digital section to keep PLL alive long enough to transition the system clock to crystal clock when Frcvco is reset by PwdnPLL or ENFE ...
Page 19
... The PLL also requires 3 numbers as for programming; Ndvsr[6:0], Nseq[7:0], and Nrst[2:0]. The following is a brief description of the registers that control the NCOs, PLLs, and sample rates for the 73M1903C IC. The tables show some examples of the register settings for different clock and sample rates. A more detailed discussion on how these values are derived can be found in Appendix B ...
Page 20
... Data Sheet Table 6: Clock Generation Register Settings for Fxtal = 24.576 MHz Reg Address Fs(kHz) 7.2 8.0 2.4*8/7*3 = 8.22857142858 8.4 9.0 9.6 2.4*10/7*3 = 10.2857142857 2.4*8/7*4 = 10.9714285714 11.2 12 12.8 2.4*10/7*4 = 13.7142857143 14.4 16.0 Table 7: Clock Generation Register Settings for Fxtal = 9.216 MHz ...
Page 21
... Reg Address Fs(kHz) 7.2 8.0 2.4*8/7*3 = 8.22857142858 8.4 9.0 9.6 2.4*10/7*3 = 10.2857142857 2.4*8/7*4 = 10.9714285714 11.2 12 12.8 2.4*10/7*4 = 13.7142857143 14.4 16.0 Table 9: Clock Generation Register Settings for Fxtal = 25.35 MHz Reg Address Fs(kHz) 7.2 16.0 Rev. 5.0 73M1903C Data Sheet Ichp (μ Dh ...
Page 22
... Figure 7 shows the block diagram of the analog front end. The analog interface circuit uses differential transmit and receive signals to and from the external circuitry. The hybrid driver in the 73M1903C is capable of connecting directly, but not limited to, a transformer- based Direct Access Arrangement (DAA). The hybrid driver is capable of driving the DAA’s line coupling transformer and load impedance ...
Page 23
... In case of Fs=9.6 kHz , then the bandwidth is 3.65 kHz x 9.6/8 = 4.38 kHz and Fs=10.28 kHz, the bandwidth is 3.65 kHz x 10.28/8 = 4.69 kHz. This is applicable for both transmit and receive path filters. Figure 8: Overall TX Path Frequency Response at 8 kHz Sample Rate Rev. 5.0 73M1903C Data Sheet 23 ...
Page 24
... Data Sheet Figure 9: Frequency Response of TX Path for kHz in Band Signal at 8 kHz Sample Rate 6.4 Transmit Levels The 16-bit transmit code word written by the DSP to the Digital Sigma-Delta Modulator (DSDM) (via TIF) has a linear relationship with the analog output signal. So, decreasing a code word by a factor of 0.5 will result ...
Page 25
... Table 10: Peak to RMS Ratios and Maximum Transmit Transmit Type Crest Factor DPSK DTMF Rev. 5.0 ( 0.001 * 600 ) ] 2 / (0.001 * 600 2.29 dBm. Levels for Various Modulation Types Max Line Level V.90 4.0 -12 dBm QAM 2.31 -9 dBm 1.81 -9 dBm FSK 1.41 -9 dBm 1.99 -5.7 dBm 73M1903C Data Sheet . pk 25 ...
Page 26
... Data Sheet 6.6 Modem Receiver A differential receive signal applied at the RXAP and RXAN pins. The DC bias for the RXAP/RXAN inputs is supplied from TXAP/TXAN thru the external DAA in normal conditions. It can be supplied internally, in the absence of the external DAA, by setting RXPULL bit in Register02. ...
Page 27
... The bandwidth of the receive filter is about 3.585 kHz when Fs=8 kHz. The bandwidth scales with Fs, the sampling rate. Refer to the Section 6.3, Modem Transmitter Rev. 5.0 73M1903C Data Sheet for more information. 27 ...
Page 28
... Data Sheet Figure 12: RXD Spectrum of 1 kHz Tone Figure 13: RXD Spectrum of 0.5 kHz, 1 kHz, 2 kHz, 3 kHz and 3.5 kHz Tones of Equal Amplitudes 28 DS_1903C_033 Rev. 5.0 ...
Page 29
... Power Saving Modes The 73M1903C has only one power conservation mode. When the ENFE, bit 7 in register 00h, is zero the clocks to the filters and the analog are turned off. The transmit pins output a nominal 80 kΩ impedance. The clock to the serial port is running and the GPIO and other registers can be read or updated ...
Page 30
... Data Sheet 8 Electrical Specifications 8.1 Absolute Maximum Ratings Operation outside these rating limits may cause permanent damage to this device. Parameter Supply Voltage Pin Input Voltage (except OSCIN) Pin Input Voltage (OSCIN) 8.2 Recommended Operating Conditions Table 13: Recommended Operation Conditions Parameter ...
Page 31
... VSS < Vin < VIL1 VIH1 < Vin < 5.5 VSS < Vin < VIL2 1 VIH2 < Vin < VDD 1 Fs=8 kHz, Xtal=27 MHz Fs=11.2 kHz, Xtal=27 MHz Fs=14.4 kHz, Xtal=27 MHz Fs=16.0 kHz, Xtal=27 MHz 73M1903C Data Sheet Nom Max Unit 0.2 * VDD V 5.5 V VDD + 0.5 V 0.45 V 0.7 V ...
Page 32
... Data Sheet 8.4 AC Timing Parameter SCLK Period (Tsclk) (Fs=8 kHz) SCLK to FS Delay (td1) SCLK to FS Delay (td2) SCLK to SDOUT Delay (td3) (With 10pf load) Setup Time SDIN to SCLK (tsu) Hold Time SDIN to SCLK (th) td1 SCLK FS SDOUT SDIN 32 Table 15: Serial Interface Timing Min – ...
Page 33
... DS_1903C_033 9 Analog Specifications 9.1 DC Specifications VREF is not brought out to a pin on the 73M1903C. This specification is for information only. The VREF voltage may be measured as the quiescent DC level at the transmit pins. Table 16: Reference Voltage Specifications Parameter VREF VDD= 3.0V - 3.6V. VREF Noise 300Hz-3.3 kHz ...
Page 34
... Data Sheet 9.3 Performance 9.3.1 Receiver Table 18: Receiver Performance Specifications Parameter Input Impedance Measured at RXAP/N relative to VREF RXPULL=HI Measured at RXAP/N relative to VREF RXPULL=LO Receive Gain Rxgain = 1; 1 kHz; RXAP/N=0.116V Boost Gain Measured relative to Rxgain=0 RXGAIN=1 for Fs=8 kHz RXGAIN =1 for Fs=12 kHz RXGAIN =1 for Fs=14 ...
Page 35
... Vbg Note: TXBST0 and DTMFBS are assumed have setting 0’s unless they are specified otherwise. Rev. 5.0 Test Condition rd and 3 harmonic. rd and 3 harmonic. rd and 3 harmonic. rd and 3 harmonic. 73M1903C Data Sheet Min Nom Max Units µv/bit 70 -100 100 MV - 1.65 DB 1.335 DB32 ...
Page 36
... C14 R16 232 3.3uF 3 2 R20 R18 150K 374 R19 49.9 C34 10uF C23 300nF R23 38K HOOK R48 100 VCCA U5 TLP627 Figure 15: 73M1903C Schematic DS_1903C_033 D2 2.4V D1 S1G C29 R17 Q3 33K MMBTA06 0.047uF + C16 Q1 BCP56 Q2 R50 MMBTA06 47k R22 R24 ...
Page 37
... Data Sheet 11 Mechanical Drawings 5 2 TOP VIEW 0.2 MIN. 0.35 / 0.45 Controlling dimensions 0.85 NOM. 3.0 / 3.75 0.18 / 0.3 1.5 / 1.875 0.25 0.5 BOTTOM VIEW 32 pin QFN Figure 16: Mechanical Drawings DS_1903C_033 / 0.9MAX. 0.00 / 0.005 0.20 REF. SEATING PLANE SIDE VIEW CHAMFERED 0 ...
Page 38
... Data Sheet 12 Ordering Information Part Description 73M1903C 32-Lead QFN Lead Free 73M1903C 32-Lead QFN, Tape and Reel, Lead Free 38 DS_1903C_033 Order Number 73M1903C-IM/F 73M1903C-IMR/F Rev. 5.0 ...
Page 39
... DS_1903C_033 Appendix A 73M1903C DAA Resistor Calculation Guide TXAP1 R1 TXAN1 RXAP R3 RXAN R2 Figure 17: Typical DAA Block Diagram The following procedure can be used to approximate the component values for the DAA with a 600 Ohm termination. With other terminations the values will be different. The optimal values will be somewhat different due to the effects of the reactive components in the DAA (this is a resistive approximation) ...
Page 40
... Data Sheet Next make the sum much higher than 600 Ω. Make sure they are lower than the input impedance of the RXAP/RXAN pins; otherwise they can move the frequency response of the input filter. So let 100 K Ω. 100 K R3 Rwtot 600 ...
Page 41
... IC. This definition is only valid when driving a specific phone line impedance. In reality, phone line impedances are never perfect, so this definition isn’t much help. Instead alternate definition that helps in analysis for this modem design, THL is the loss from the transmit pins to the receive pins. Rev. 5 73M1903C Data Sheet ZL 41 ...
Page 42
... Data Sheet Appendix B Crystal Oscillator The crystal oscillator is designed to operate over wide choice of crystals (from 4.9 MHz to 27 MHz). The crystal oscillator output is the input to an NCO based pre-scaler (divider) prior to being passed onto an on-chip PLL. The intent of the pre-scaler is to convert the crystal oscillator frequency, Fxtal convenient frequency to be used as a reference frequency, Fref, for the PLL. A set of three numbers– ...
Page 43
... Fref PFD Ichp Control 73M1903C has a built in PLL circuit to allow an operation over wide range of Fs conventional design with the exception of an NCO based feedback divider. See Figure 19. The architecture of the 73M1903C dictates that the PLL output frequency, Fvco, be related to the sampling rate, Fs, by Fvco = 2 x 2304 x Fs. The NCO must function as a divider whose divide ratio equals Fref/Fvco. Just as in the NCO prescaler, a set of three numbers– ...
Page 44
... Three separate controls are provided to fine-tune the PLL as shown in the following sections. To ensure quick settling of PLL, a feature was designed into the 73M1903C where Ichp is kept at a higher value until LockDet becomes active or Frcvco bit is set to 1, whichever occurs first. Thus, PLL is guaranteed to have the settling time of less than one Frame Synch period after a new set of NCO parameters had been written to the appropriate registers ...
Page 45
... Fvco = 2 x 2304 2304 x 2.4 kHz x 8 50.55634 MHz. Step 2. Express the required VCO frequency divided by the Crystal Frequency as a ratio of two integers. This is initially given by : • • 2 2304 2.4kHz = Fvco / Fxtal 24 . 576 Rev. 5.0 • • 8 MHz 73M1903C Data Sheet 45 ...
Page 46
... Data Sheet After a few rounds of simplification this ratio reduces to Fvco / Fxtal ( 35 Nnco1 Dnco1 = Nnco2 Dnco2 , where Nnco1 and Nnco2 must be < or equal to 8. The ratio, Nnco1/Dnco1 = 4/35, is used to form a divide ratio for the NCO in pre-scaler and Nnco2/Dnco2 =1/18 for the NCO in the PLL. ...
Page 47
... Pseq = {x,x,x,x,x,x,x,x}= xxh. PLL NCO: From Nnco2/Dnco2 = 1/24, Ndvsr = Integer [ Dnco2/Nnco2 ] = 24 = 18h, Nrst[2:0] = Nnco2 – this means NO fractional divide. It always does ÷24. Thus, Nseq becomes “don’t care”. Nseq = {x,x,x,x,x,x,x,x} = xxh. Rev. 5.0 • • 2.4kHz 20 576 MHz 73M1903C Data Sheet 47 ...
Page 48
... Data Sheet Revision History Rev. # Date 4.3 1/17/2008 5.0 3/9/2010 © 2010 Teridian Semiconductor Corporation. All rights reserved. Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation. Simplifying System Integration is a trademark of Teridian Semiconductor Corporation. MicroDAA is a registered trademark of Teridian Semiconductor Corporation. ...