M052LAN Nuvoton Technology Corporation of America, M052LAN Datasheet - Page 315

• Manufacturer Part Number: M052LAN
• Description: IC MCU 32BIT 8KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro M051™r

Specifications of M052LAN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 40
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.11.4.5 Single-Cycle Scan Mode
NuMicro M051
1.
2.
3.
4.
Note: If software enables more than one channel in burst mode,
converted and other enabled channels will be ignored.
In single-cycle scan mode, A/D conversion will sample and convert the specified channels once in
the sequence from the least to highest channel. Operations are as follows:
1.
2.
3.
4.
An example timing diagram for single-cycle scan on enabled channels (0, 2, 3 and 7) is shown in
the
When the ADST bit in ADCR is set to 1 by software or external trigger input, A/D conversion
starts on the channel with the lowest number.
When A/D conversion for special enabled channel is completed, the result is sequentially
transferred to FIFO and can be accessed from the A/D data register 0.
When more than 4 samples in FIFO, the ADF bit in ADSR is set to 1. If the ADIE bit is set to
1 at this time, an ADINT interrupt is requested after A/D conversion ends.
Steps 2 to 3 are repeated as long as the ADST bit remains set to 1. When the ADST bit is
cleared to 0, A/D conversion stops and the A/D converter enters the idle state.
When the ADST bit in ADCR is set to 1 by a software or external trigger input, A/D
conversion starts on the channel with the lowest number.
When A/D conversion for each enabled channel is completed, the result is sequentially
transferred to the A/D data register corresponding to each channel.
When conversion of all the selected enabled channels is completed, the ADF bit in ADSR is
set to 1. If the ADIE bit is set to 1 at this time, an ADINT interrupt is requested after A/D
conversion ends.
After A/D conversion ends, the ADST bit is automatically cleared to 0 and the A/D converter
enters idle state. If ADST is cleared to 0 before all enabled ADC channels conversion done,
ADC controller will finish current conversion and the result of the lowest enabled ADC
channel will become unpredictable.
™
Series Technical Reference Manual
- 315 -
Publication Release Date: Sept 14, 2010
the channel with the lowest number
Revision V1.2
is