DS92LV0412SQE/NOPB National Semiconductor, DS92LV0412SQE/NOPB Datasheet - Page 7

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DS92LV0412SQE/NOPB

Manufacturer Part Number
DS92LV0412SQE/NOPB
Description
IC SER/DESER 5-50MHZ 24B 48-LLP
Manufacturer
National Semiconductor
Datasheet

Specifications of DS92LV0412SQE/NOPB

Serdes Function
Deserializer
Data Rate
1.2Gbps
Ic Output Type
CML
No. Of Inputs
2
No. Of Outputs
4
Supply Voltage Range
1.71V To 1.89V, 3V To 3.6V
Driver Case Style
LLP
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DS92LV0412SQE/NOPBTR
Pin Name
Optional Serial Bus Control
ID[x]
SCL
SDA
Power and Ground (see NOTE below)
VDDL
VDDA
VDDP
VDDSC
VDDTX
VDDIO
GND
DAP
NOTE: 1= HIGH, 0 = LOW
The VDD (V
on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.
39, 44, 45, 48
9, 14, 26, 32,
DDn
38, 43
46, 47
Pin #
6, 31
DAP
and V
12
13
25
5
4
8
DDIO
) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor
I/O, LVCMOS
I, LVCMOS
Open Drain
Open Drain
I/O, Type
I, Analog
Ground
Ground
Power
Power
Power
Power
Power
Power
Description
Serial Control Bus Device ID Address Select — Optional
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See .
Serial Control Bus Clock Input - Optional
SCL requires an external pull-up resistor to 3.3V.
Serial Control Bus Data Input / Output - Optional
SDA requires an external pull-up resistor 3.3V.
Logic Power, 1.8 V ±5%
Analog Power, 1.8 V ±5%
PLL Power, 1.8 V ±5%
SSC Generator Power, 1.8 V ±5%. Power must be connected to these pins regardless if
the SSCG feature is used or not.
Channel Link LVDS Parallel Output Power, 3.3 V ±10%
LVCMOS I/O Power and Channel Link I/O Power 1.8 V ±5% OR 3.3 V ±10%
Ground
DAP is the large metal contact at the bottom side, located at the center of the LLP
package. Connect to the ground plane (GND) with at least 9 vias.
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