DS90UB903QSQX/NOPB National Semiconductor, DS90UB903QSQX/NOPB Datasheet - Page 26

• Manufacturer Part Number: DS90UB903QSQX/NOPB
• Description: IC SER/DESER 10-43MHZ 18B 40LLP
• Manufacturer: National Semiconductor

Specifications of DS90UB903QSQX/NOPB

• Function: Serializer
• Data Rate: 900Mbps
• Input Type: LVCMOS
• Output Type: CML
• Number Of Inputs: 1
• Number Of Outputs: 1
• Voltage - Supply: 1.71 V ~ 1.89 V, 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 40-WFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Functional Description
The DS90UB903Q/904Q FPD-Link III chipset is intended for
video display applications. The Serializer/ Deserializer
chipset operates from a 10 MHz to 43 MHz pixel clock fre-
quency. The DS90UB903Q transforms a 21-bit wide parallel
LVCMOS data bus along with a bidirectional control bus into
a single high-speed differential pair. The high-speed serial bit
stream contains an embedded clock and DC-balance infor-
mation which enhances signal quality to support AC coupling.
The DS90UB904Q receives the single serial data stream and
converts it back into a 21-bit wide parallel data bus together
with the bidirectional control channel data bus.
The control channel function of the DS90UB903Q/904Q pro-
vides bidirectional communication between the host proces-
sor and display. The integrated control channel transfers data
simultaneously over the same differential pair used for video
data interface. This interface offers advantages over other
chipsets by eliminating the need for additional wires for pro-
gramming and control. The control supports I
SERIAL FRAME FORMAT
The DS90UB903Q/904Q chipset will transmit and receive a
pixel of data in the following format:
The High Speed Forward Channel is a 28-bit symbol com-
posed of 21 bits of data containing video data & control
information transmitted from Serializer to Deserializer. CLK1
and CLK0 represent the embedded clock in the serial stream.
CLK1 is always HIGH and CLK0 is always LOW. This data
payload is optimized for signal transmission over an AC cou-
pled link. Data is randomized, balanced and scrambled.
The bidirectional control channel data is transferred along
with the high-speed forward data over the same serial link.
This architecture provides a full duplex low speed forward
channel across the serial link together with a high speed for-
ward channel without the dependence of the video blanking
phase.
FIGURE 22. Serial Bitstream for 28-bit Symbol
FIGURE 21. Typical Display System Diagram
2
C port. The
26
bidirectional control channel offers asymmetrical communi-
cation and is not dependent on video blanking intervals.
DISPLAY APPLICATION
The DS90UB903Q/904Q chipset is intended for interface be-
tween a host (graphics processor) and a Display. It supports
a 21 bit parallel video bus for 18-bit color depth (RGB666)
display format. In a RGB666 configuration, 18 color bits (R
[5:0], G[5:0], B[5:0]), Pixel Clock (PCLK) and three control bits
(VS, HS and DE) are supported across the serial link.
The DS90UB903Q Serializer accepts a 21-bit parallel data
bus along with a bidirectional control bus. The parallel data
and bidirectional control channel information is converted into
a single differential link. The integrated bidirectional control
channel bus supports I2C compatible operation for controlling
auxiliary data transport to and from host processor and dis-
play module. The DS90UB904Q Deserializer extracts the
clock/control information from the incoming data stream and
reconstructs the 21-bit data with control channel data.
DESCRIPTION OF BIDIRECTIONAL CONTROL BUS AND
I2C MODES
The I
DS90UB903Q, DS90UB904Q, or an external remote device
(such as a display) through the bidirectional control channel.
Register
DS90UB903Q/904Q chipset are employed through the clock
(SCL) and data (SDA) lines. These two signals have open-
drain I/Os and both lines must be pulled-up to VDDIO by
external resistor.
the clock (SCL) and data (SDA) signals. Pull-up resistors or
current sources are required on the SCL and SDA busses to
pull them high when they are not being driven low. A logic zero
is transmitted by driving the output low. A logic high is trans-
2
C compatible interface allows programming of the
programming
Figure 4
shows the timing relationships of
transactions
to/from
30125461
30125406
the