73M1822-IM/F Maxim Integrated Products, 73M1822-IM/F Datasheet
73M1822-IM/F
Specifications of 73M1822-IM/F
Related parts for 73M1822-IM/F
73M1822-IM/F Summary of contents
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... Simplifying System Integration™ DS_1x22_001 DESCRIPTION The 73M1822 MicroDAA is the world’s first single-package silicon Data Access Arrangement (DAA) for data/fax modem and voice applications. It provides a serial Modem Analog Front End (MAFE) interface to popular DSP/host processors to implement a globally compliant low-cost soft modem solution ...
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... Detectors ............................................................................................................................... 27 3.13.1 Over-Voltage Detector................................................................................................. 27 3.13.2 Over-Current Detector ................................................................................................. 27 3.13.3 Under-Voltage Detector............................................................................................... 27 3.13.4 Over-Load Detector..................................................................................................... 27 4 Applications Information ................................................................................................................ 28 4.1 Example Schematic of the 73M1922 and 73M1822 ................................................................ 28 4.2 Bill of Materials ...................................................................................................................... 30 4.3 Over-Voltage and EMI Protection ........................................................................................... 31 4.4 Isolation Barrier Pulse Transformer ........................................................................................ 32 5 Control and Status Registers ......................................................................................................... 33 5 ...
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... AC Signal Over Load Detection.............................................................................................. 71 12.11 Over Current Detection (OID) ................................................................................................. 71 12.12 Line Status Functions Control Functions ................................................................................ 72 13 Loopback and Testing Modes ........................................................................................................ 75 14 Performance ................................................................................................................................... 77 14 Characteristics ............................................................................................................. 77 14.2 Receive ................................................................................................................................. 78 15 Package Layout .............................................................................................................................. 79 16 Ordering Information ...................................................................................................................... 81 17 Contact Information ........................................................................................................................ 81 Revision History ..................................................................................................................................... 82 Rev. 1.6 73M1822/73M1922 Data Sheet 3 ...
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... Figure 8: Call Progress Monitor Frequency Response ............................................................................... 20 Figure 9: Demo Board Circuit Connecting AOUT to a Speaker .................................................................. 20 Figure 10: Recommended Circuit for the 73M1922 ................................................................................... 28 Figure 11: Recommended Circuit for the 73M1822 ................................................................................... 29 Figure 12: Suggested Over-voltage Protection and EMI Suppression Circuit ............................................. 31 Figure 13: Clock Generation Block Diagram (assumes 8 kHz sample rate) ............................................... 41 Figure 14: Crystal Oscillator with Configurable Load Current ...
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... Table 21: Receive Notch Filter .................................................................................................................. 26 Table 22: Over-Voltage Detector ............................................................................................................... 27 Table 23: Over-Current Detector ............................................................................................................... 27 Table 24: Under-Voltage Detector ............................................................................................................. 27 Table 25: Over-Load Detector ................................................................................................................... 27 Table 26: Reference Bill of Materials for 73M1822/73M1922 ..................................................................... 30 Table 27: Reference Bill of Materials for Figure 12 .................................................................................... 31 Table 28: Compatible Pulse Transformer Sources .................................................................................... 32 Table 29: Transformer Characteristics ...................................................................................................... 32 Table 30: Control and Status Register Map ............................................................................................... 33 Table 31: Alphabetical Bit Map ...
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... Host-Side and Line-Side Devices includes the media stream data, control, status and clocking information. The data sheet describes both the 73M1922 and 73M1822, which will be collectively referred to as the 73M1x22 in this document. The Host-Side Device uses a serial data port for transferring transmit and receive data, status and control information to a host ...
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... DS_1x22_001 The Line-Side Device (73M1912 / 73M1822) consists of: 1. Digital Sigma Delta Modulator (DSDM) 2. Transmit Analog Front End (TxAFE) 3. Receive Analog Front End (RxAFE) including Sigma Delta Modulator (ASDM) 4. Sinc^3 Filter (Sinc3) 5. On-chip Line Interface Circuit (ONLIC) 6. Line-Side Barrier Interface Circuit (LSBI) The transmit data (TxData) is interpolated up within TIF (Transmit Interpolation Filter) from the sampling frequency (Fs) to twice the sampling frequency resulting in TxD ...
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... Data Sheet 2 Pinout The 73M1922 consists of two devices, the 73M1902 and the 73M1912, which are available as 20-pin TSSOP packages and as 32-pin QFN package sets. 2.1 73M1902 20-Pin TSSOP Pinout Figure 2 shows the 73M1902 20-pin TSSOP pinout. FSD FS VND VPD/VPPLL OSCIN/MCLK ...
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... Ring detection indicator or other Interrupts O Open drain Serial interface clock. With continuous SCLK selected, O Frequency = 256∗Fs (=1.8432MHz for Fs=7.2kHz, 2.048MHz for Fs=8kHz) Negative digital ground I Serial data input (or output from the controller to 73M1902) O Serial data output (or input to the controller from 73M1902) 73M1822/73M1922 Data Sheet 9 ...
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... Data Sheet 2.2 73M1912 20-Pin TSSOP Pinout Figure 3 shows the 73M1912 20-pin TSSOP pinout. DCI RGN RGP OFH VND/VNX SCP MID VPX SRE SRB Figure 3: 73M1912 20-Pin TSSOP Pinout Table 2 describes the pin functions for the device. Decoupling capacitors on the power supplies should be included for each pair of supply pins ...
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... Negative analog/PLL ground Negative analog/PLL ground O Band gap voltage reference monitor O Call progress audio output O Digital test output Type of frame sync late (mode0 early (mode1). I Weak-pulled high – default = early. Positive analog supply 73M1822/73M1922 Data Sheet 24 VND 23 SCLK INT/RGDT 22 LEV 21 20 VPT/VPD RST ...
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... Data Sheet Pin Pin Name Type Number 14 SCKM 15 VNM/VNT GND 16 M/S 17 PRM I/O 18 PRP I/O RST 19 20 VPD PWR 21 LEV INT/RGDT 22 23 SCLK 24 VND GND 25 SDIN 26 SDOUT 27 VPD PWR FSD VND GND 31 GPIO7 I/O 32 GPIO6 I/O 12 Description Controls the SCLK behavior after FS. Weak-pulled high – ...
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... External rectification – disables internal rectifier when low, leave open Factory test mode – leave open Voltage regulator sense Voltage regulator drive Analog/digital negative supply voltage VBG bypass, connect to 0.1μF capacitor to VPS AC current sense Analog/digital negative supply voltage 73M1822/73M1922 Data Sheet 24 DCD 23 RST TST 22 21 TXM ...
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... Data Sheet Pin Pin Type Number Name 17 VPS PWR 18 RXP I 19 RXM I 20 SACIN I 21 TXM O TST 22 I RST DCD O 25 DCS I 26 DCG O 27 DCI I 28 RGN I 29 RGP I 30 VNS GND 31 GPI I 32 GPO O 14 Description Analog/digital positive supply voltage Receive plus – ...
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... Open drain Serial interface clock. With continuous SCLK selected, O Frequency = 256∗Fs (=1.8432 MHz for Fs=7.2 kHz, 2.048 MHz for Fs=8 kHz) I Serial data input (or output from the controller to the 73M1822) O Serial data output (or input to the controller from the 73M1822 delayed O ...
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... Exposed Bottom Pad on 73M1x66B QFN Packages The 73M1822 and 73M1922 QFN packages have exposed pads on the underside that are intended for device manufacturing purposes. These exposed pads are not intended for thermal relief (heat dissipation) and should not be soldered to the PCB. Soldering of the exposed pad could also compromise electrical isolation/insulation requirements for proper voltage isolation ...
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... Recommended Operating Conditions Function operation should be restricted to the recommended operating conditions specified in Table 8. Table 8: Recommended Operating Conditions Parameter Supply voltage (VDD) with respect to VSS Operating temperature Rev. 1.6 73M1822/73M1922 Data Sheet Rating 768 kHz 1.536 Mbps Min Max Unit -0.5 4 ...
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... Data Sheet 3.2.3 DC Characteristics Table 9 lists the 73M1x22 DC characteristics. Parameter Input low voltage VIL Input high voltage VIH1 (except OSCIN) Input High Voltage VIH2 OSCIN Output low voltage VOL (except OXCOUT, FS, SCLK, SDOUT) Output low voltage VOLOSC OSCOUT Output Low Voltage ...
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... Hz – 3.3 kHz VBG PSRR 300 Hz – 30 kHz Rev. 1.6 Min – 1/1.536 MHz – – – – – Figure 7: MAFE Timing Diagram Min 0.9 – 40 73M1822/73M1922 Data Sheet Nom Max Unit – ns – – – – – ns – – ...
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... Data Sheet 3.4.2 Call Progress Monitor The Call Progress Monitor monitors activities on the line. The audio output contains both transmit and receive data with a configurable level individually set by Register 0x10. Figure 8 shows the frequency response of the Call Progress Monitor Filter based upon the characteristics of the device plus the external circuitry as shown ...
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... Vpk at RXP/RXM with RXG=10 (+6 dB) CMTXG=11(Mute) Observe AOUT pin CMRXG=00 CMRXG=01 relative to CMRXG=00 CMRXG=10 relative to CMRXG=00 CMRXG=11(Mute) AOUT receive THD CMRXG=00 AOUT output – impedance Rev. 1.6 73M1822/73M1922 Data Sheet n Min Nom Max Units – – – – – 0.98 – Vpk – -6 – ...
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... Data Sheet 3.5 73M1x22 Line-Side Electrical Specifications (73M1912) Table 14 lists the absolute maximum ratings for the line side. Operation outside these rating limits may cause permanent damage to this device. Table 14: Line-Side Absolute Maximum Ratings Parameter Pin input voltage from VPX to VNX Pin input voltage (all other pins) to VNS 3 ...
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... DCI I after ILIM ILM=1 V DCI DCI At the line with 300 Ω(ac) (0.15 - 4.0 kHz) *Noise Rev. 1.6 <0.4V+V DCON =0.28V+V DCON =0.44V+V DCON 73M1822/73M1922 Data Sheet Min Nom Max Units 0.69 0.73 0.78 0.89 0.94 0.99 1.01 1.06 1.11 1.13 1.18 1 ...
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... Data Sheet 3.9 Transmit Path Table 18 lists the transmit path characteristics. A pattern for a sinusoid of 1 kHz, full scale (code word of +/- 32,767) from the 73M1x22 is forced and ACS is measured with R10=255 Ω. Test conditions are: ACZ=00 (600 Ω termination), THEN=1, ATEN=1, DAA=01, TXBST=0. ...
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... Barrier Powered Mode; 300 Hz – 30 kHz. Rev. 1.6 Table 19: Receive Path Min – – – 43 – – 17.5 – -0.25 – – – – – – 40 – 73M1822/73M1922 Data Sheet Nom Max Units kΩ 1000 – 1.0 1.16 Vpk 1. µV/bit – ...
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... Data Sheet 3.11 Transmit Hybrid Cancellation Table 20 lists the transmit hybrid cancellation characteristics. Unless stated otherwise, test conditions are: ACZ=00 (600 Ω termination), THEN=1, ATEN=1, DAA=01, TXBST=0. TXM is externally fed back into the 73M1912 to effect cancellation of transmit signal. Table 20: Transmit Hybrid Cancellation Characteristics ...
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... Measured at DCI with 1 kHz. Rev. 1.6 Table 22: Over-Voltage Detector Min 0.52 0.59 Table 23: Over-Current Detector Min 0.85 Table 24: Under-Voltage Detector Min 5.6 Table 25: Over-Load Detector Min 0.6 73M1822/73M1922 Data Sheet Nom Max Unit 0.6 0.68 V 0.7 0.77 V Nom Max Unit 0.96 1.10 ...
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... Example Schematic of the 73M1922 and 73M1822 Figure 10 shows a reference schematic for the 73M1922. Figure 11 shows a reference schematic of the 73M1822. Note that minor changes may occur to the reference material from time to time and the reader is encouraged to contact Teridian for the latest information. For more information about schematic and layout design, see the 73M1822/73M1922 Schematic and Layout Guidelines ...
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... C4 U1 10uF 1 4 C13 15pF C24 NC (1nF, 3kV C14 T1 15pF C30 1nF Isolation Barrier Figure 11: Recommended Circuit for the 73M1822 73M1822/73M1922 Data Sheet R66 1M C1 0.022uF (200V, 1206) R67 1M C3 0.022uF (200V, 1206) BR1 1 + HD04 Q4 MMBTA42 1 MMBTA92 R2 1 10M ...
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... R66, R67 1 M,1/8W resistor 0805 R69* 100K typ. 5%, 1/10W resistor 0603 T1 Pulse transformer Y1 24.576 MHz crystal (fundamental) * Optional – see the 73M1822/73M1922 Schematic and Layout Guidelines for details. 30 Example Source Example MFR P/N Diodes Inc. HD04-T Panasonic ECJ-3FB2D223K AVX, Panasonic ...
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... C36, C35 220 pF, 3000 V C42 220 pF, 300 V Rev. 1.6 L1 Ω F1 2000 @ 100 MHz TR600-150 E1 P3100SBRP L2 Ω 2000 @ 100 MHz C35 220 pF, 3000 V Source Diodes, Inc. Bourns Steward/TDK TDK Vishay 73M1822/73M1922 Data Sheet RJ-11 Example MFR P/N TB3100H-13-H MF-R015/600 or equivalent MPZ2012S601A C4532COG3F221K VJ1206Y221KXEAT5Z 31 ...
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... Data Sheet 4.4 Isolation Barrier Pulse Transformer The isolation element used by the 73M1x22 is a standard digital pulse transformer. Several vendors supply compatible transformers with up to 6000 V ratings. Since the transformer is the only component crossing the isolation barrier other than EMI capacitors that may be required, it solely determines the isolation between the PSTN and the 73M1922 digital interface ...
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... DS_1x22_017 5 Control and Status Registers Table 30 shows the register map of addressable registers for the 73M1822 and 73M1922. The shaded cells in the register map indicate read only and cannot be modified. Reserved bits should be left in their default state. Accessing unspecified registers should be avoided. Each register and bit is described in detail in the following sections ...
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... Data Sheet Throughout this document, type W is read/write, type WO is write only and type R is read only. Registers and bits are defined as 0x16[3:0], where 0x16 is the register address and the numbers in square brackets specify the address bits. The bit order is [msb – lsb] for a field. For example, [3:0] means bits 3 through particular field ...
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... Barrier Control Function 0 W Barrier Control Function 0 W MAFE Configuration 0 R Barrier Control Function 0 W DAA Control Function 0 W Loopback Controls 0 W Loopback Controls 0 WO Signal Control Function 0 WO Signal Control Function 0 R DAA Control Function 11 W Device Clock Management 73M1822/73M1922 Data Sheet 35 ...
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... Data Sheet 5.1 Line-Side Device Register Polling The Register Map as read from a 73M1x22 Host-Side Device consists of two groups. The first is the Host-Side Device registers (0x00 through 0x11) and the second is a copy of the Line-Side Device registers (0x12 through 0x1F extra degree of integrity the 73M1x22 supports the ability to manually monitor the registers of its Line- Side Device ...
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... Device Revision The 73M1922 provides the device revision number for the Host-Side Device and the Line-Side Device. For the 73M1822B07 and 73M1922A01 (73M1902B04) Host-Side Device, the current revision is 0111. For the 73M1822B07 and 73M1922A01 (73M1912B07) Line-Side Device, the current revision is 1001. ...
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... Data Sheet 6.3 Power Management The 73M1x22 supports three modes of power control for the device. Normal mode The 73M1x22 operates normally. Sleep mode The device PLL is turned off and the internal clock is driven by Xtal. SCK=1/8 Xtal. Control and status registers maintain their content. ...
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... GPIO Registers The 73M1922 32-pin QFN package provides four I/O pins (GPIO7, GPIO6, GPIO5 and GPIO4). The 73M1822 (42-pin QFN package) provides one user GPIO pin (GPIO6). GPIO pins are not available on the 20-pin package version of the 73M1922. Each pin can be configured independently as either an input or an output. ...
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... Data Sheet 6.6 Call Progress Monitor For the purpose of monitoring activities on the line, a Call Progress Monitor is provided in the 73M1x22. This audio output contains both transmit and receive data with configurable levels. Function Register Type Mnemonic Location CMVSEL 0x10[4] W CMTXG 0x10[3:2] ...
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... Figure 14: Crystal Oscillator with Configurable Load Current Table 5: Crystal Oscillator Load Current versus XIB Rev. 1.6 FrcVco 4608 Fs= 36.864 MHz Fref Prescalar PLL NCO XIB(1:0) OSCOUT OSCIN XIB Load Current 120 μA 00 180 μA 01 270 μA 10 450 μA 11 73M1822/73M1922 Data Sheet Sysclk = 36.864 MHz or Xtal Freq PwdnPLL 41 ...
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... Data Sheet 7.3 PLL Prescaler The prescaler converts the crystal oscillator frequency, Fxtal convenient frequency to be used as a reference frequency, Fref, for the PLL. A set of three numbers must be entered through the serial port – PDVSR (5 bit), PRST (3 bit) and PSEQ (8 bit) as follows: ...
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... Data Sheet NRST Ichp KVCO (μA) 0x0D (2:0) 0x04 8 0 0x02 10 1 0x04 0x00 8 4 0x04 12 6 0x04 ...
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... Data Sheet Table 35: Clock Generation Register Settings for Fxtal = 24.000 MHz Bit, Reg Address PSEQ Fs (kHz) 7.2 8.0 9.6 12 14.4 16.0 Table 36: Clock Generation Register Settings for Fxtal = 25.35 MHz Bit, Reg Address PSEQ Fs(kHz) 7 PRST, ICHP, PDVSR KVCO_H NDVSR ...
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... This bit is recommended to be set to 1 for the applications requiring dynamic sample rate changes such as V.34 and V.90 modems, etc. W Represents the rate at which the NCO sequence register is reset. 73M1822/73M1922 Data Sheet KVCOH0 Fvco Kvco 0 33 MHz ...
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... The slave device can be of either an early or late type. For every data Fs, 16 bits are transmitted and 16 bits are received. The standard 73M1822 device supports the late frame sync mode only need for a frame sync early mode is required, contact the Teridian Marketing department for details. ...
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... Bit 6 Bit Bit 8 Bit 7 Bit 6 Bit KHz Control Frame 73M1822/73M1922 Data Sheet Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TX4 TX3 TX2 TX1 CTL Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TX4 TX3 TX2 TX1 TX0 Bit 4 Bit 3 Bit 2 Bit 1 Bit Bit 4 Bit 3 Bit 2 Bit 1 ...
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... SCLK is a continuous clock running at 256∗Fs (Fs = Sample rate frequency). On the 32-pin version of 73M1922, the SCKM (Pin 14), which is weakly pulled high internally, can be connected to ground to stop the SCLK after 32 clock cycles. This is illustrated in Figure 20. The 73M1822 and 73M1922 20-pin TSSOP packages only support the continuous SCLK configuration. Table 38: Behavior of SCLK under SCKM ...
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... The M/S pin is used to provide reset in the 73M1822 and 72M1902 20-pin TSSOP packaged parts. The reset signal is also bi-directional and edge triggered, so either a low-to-high or high-to-low transition will generate a reset. Ensure the final state of M/S is the master or slave mode that is desired ...
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... Data Sheet 8.6 73M1x22 in Daisy Chain Configuration An internal register controls the daisy chain mode. FS pin of a slave device is an input from the FSD pin of the preceding device. In this arrangement, the HC bit (Register 0x02[0]) is ignored and the Software control is automatically enabled. Setting CTL (bit 0 of the SDIN data stream does the control frame request. The delayed FS, FSD, is fed to the subsequent slave device as FS ...
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... SDOUT data stream. (Default) Daisy Chain FSD Latency Control FSD delay is 32 SCLK periods. (Default FSD delay is 16 SCLK periods. This bit must be set when there are four or more slave devices. When a master is driving a slave, only Early Type is allowed. 73M1822/73M1922 Data Sheet 51 ...
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... Transmit Path Signal Processing 9.1.1 General Description In the transmit path, data is first sent by the host DSP through a serial interface to the 73M1822 / 73M1922 then interpolated by a transmit interpolation filter, serialized and transmitted across to the Line-Side Device, which is floating relative to the Host-Side Device earth ground. The data received on the Line-Side Device is then de-serialized and digitally sigma-delta modulated to a one-bit data stream of 1 ...
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... The frequency response and bandwidth of the receive path is dependent on the sampling frequency (Fs). Figure 28 and Figure 29 show the normalized frequency response of the receive path, including the effect of the decimation filter in the 73M1902/73M1822 HIC. For Fs=8 kHz, the 0.2 dB pass-band ripple frequency is from DC to 3.342 kHz. The 3 dB bandwidth is 3 ...
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... Data Sheet 9.2.2 Total Receive Path Response Figure 28: Overall Frequency Response of the Receive Path Figure 29: Pass-band Response of the Overall Receive Path 54 DS_1x22_017 Rev. 1.6 ...
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... Sets the receive path gain/attenuation. See Table 41. Transmit Path Enable 1 = Enable Transmit Path Disable Transmit Path. (Default) Receive Path Enable 1 = Enable Receive Path Disable Receive Path. (Default) Table 40: Transmit Gain Control TXBST DAA1 DAA0 Gain, nom. Units + -2.0 73M1822/73M1922 Data Sheet ...
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... Data Sheet On the receive side, there are two RXG bits RXG(1:0) (Register 0x14[1:0]) to control the receive gain. The RXG bits need to be set to 00. When the received line signal exceeds the voltage specified in ITU-T Recommendation G.712 (2001), the receive gain must be reduced to prevent saturation and clipping within the receive signal processing path ...
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... When loss of synchronization is detected, the SLHS bit is set to 1 and likewise SYNL is also set to 1 and initiates an interrupt to the host. Once the SYNL bit is asserted a new barrier synchronization sequence will automatically begin. Once read, the SLHS bit is reset, but will be set again if the synchronization loss continues. Rev. 1.6 73M1822/73M1922 Data Sheet 57 ...
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... Auxiliary A/D Converter Line monitoring and sensing is performed with an 8-bit auxiliary A/D converter integrated in the 73M1922/73M1822. The input signals are connected to RGP and RGN pins. In certain applications, this A/D can be used to sample signals unrelated to PSTN DAA functions. In this type of application necessary to isolate the input signal with optical or other means since the 73M1x22 is connected directly to the PSTN and is susceptible to high voltage surge ...
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... Enables No-Transition Timer of 400 µs. (Default Disables No-Transition Timer. Synchronization Loss Line Side 0 = TXRDY will continuously be generated following Synchronization Loss allow information to be transferred across the SLLS barrier. This causes an automatic transfer of 1Eh. (Default Synchronization is lost in the Line-Side Device due to Header. 73M1822/73M1922 Data Sheet 59 ...
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... Data Sheet 10.7 Line-Side Device Operating Modes The architecture of the 73M1x22 is unique in that the isolation barrier device, an inexpensive pulse transformer, is used to provide power and also bidirectional data between the Host-Side Device and the Line-Side Device. When the 73M1x22 is on hook, all the power for the Line-Side Device is provided over the barrier interface ...
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... DC current supplied by the line. There are four settings that can be used to set the voltage to current ratio. Figure 31 shows the DC-IV characteristics of the 73M1x22 with special regions of interest. Programmable Turn-on Voltage Rev. 1.6 V Current Limit Turned on 41 Ω * Seize Voltage * ~50 Ω with 8 Ω fuse resistance Current Limit Turn-on=42 mA Figure 31: DC-IV Characteristics 73M1822/73M1922 Data Sheet 2.2 kΩ ...
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... Data Sheet The 73M1x22 can: • Shift the characteristics by setting the turn-on voltage. • Enable a current limit of 42 mA. The 73M1x22 meets a wide range of different countries’ requirements under software control. See Section 11.7. There are two operating states for the DC-IV circuits: Hold and Seize. ...
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... Figure 34 shows magnitude response of the impedance matching filter for the case of ETSI ES 203 021- approximately equal to the inverse of the frequency characteristics of the impedance being realized. Rev. 1.6 DCVI Performance DCIV=xx Australian Not Recommended Region current, mA 73M1822/73M1922 Data Sheet 80 90 100 63 ...
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... Data Sheet ⋅ F1db f 1000 ( ) Figure 34: Magnitude Response of IPMF, ACZ=01 (ETSI ES 203 021-2) 11.4 Billing Tone Rejection Some countries use a large amplitude out-of-band tone to measure call duration to allow remote central offices to determine the duration of a call for billing purposes. To avoid saturation and distortion of the input caused by these tones important to be able to reject them ...
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... In addition, ENNOM=0 prevents the reset of all bits in Register 0x12. (Default Enter Nominal Operation. Reduces the loop bandwidth of the DC transconductance circuit. Allows reset of Register 0x12 caused by bits UVDT, OVDT or OIDT. 73M1822/73M1922 Data Sheet Min Nom Max Units ...
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... Data Sheet Function Register Type Mnemonic Location DCIV 0x13[7:6] WO Current Limiting Detection Control and Status ILM 0x13[5] WO ILMON 0x1E[7] R THDCEN 0x13[4] W ATEN 0x16[ Description DC Current Voltage Characteristic Control Hold state with ENDC and ENAC= loop current except if the DC-IV curve is shifted to a value given by these bits. This assumes that there is a 5:1 attenuation of off-hook ...
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... Analog Power Save Enable 0 = Saves analog power in LIC of 73M1822 or 73M1912 Full analog power in LIC of 73M1822 or 73M1912. Receive Low Pass Notch Enable 0 = Billing Tone Receive Low Pass Notch (RLPN) filter bypassed. (Default RLPN Filter Enabled ...
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... Data Sheet Function Register Type Mnemonic Location ACCEN 0x13[4] W ENAC 0x12[5] WO ENDC 0x12[6] WO ENSHL 0x12[4] WO ENFEL 0x12[2] WO ENLVD 0x12[ Description AC Cancellation Enable Cancels the AC signals from the DC transconductance circuit cancellation. (Default Enables the cancellation of AC from the DC transconductance circuit. This should be set for normal operation. ...
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... Luxembourg Macao Malaysia Malta Mexico Morocco Netherlands New Zealand Nigeria Norway 01 10 Oman 00 10 73M1822/73M1922 Data Sheet Country ACZ DCIV Pakistan 00 10 Peru 00 10 Philippines Poland Portugal Romania 01 10 Russia Saudi Arabia 00 10 Singapore Slovakia Slovenia 01 10 South Africa 11 10 South Korea ...
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... Data Sheet 12 Line Sensing and Status 12.1 Auxiliary A/D Converter An 8-bit auxiliary A/D converter integrated in the 73M1x22 provides line monitoring and sensing capabilities. The A/D converter input signals are connected to the RGP and RGN pins of the device possible to use this A/D converter to sample signals unrelated to PSTN DAA functions. However, in this application necessary to isolate the input signal with optical or other means since the 73M1x22 is connected directly to the PSTN ...
Page 71
... Vpk. 12.11 Over Current Detection (OID) When the line current exceeds the safe operating range of the 73M1x22 or the external transistors, the device indicates this condition. If enabled, the 73M1x22 will automatically go on-hook if an over current event is detected. Rev. 1.6 73M1822/73M1922 Data Sheet 71 ...
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... Data Sheet 12.12 Line Status Functions Control Functions These registers contain control information to set up and use the 73M1x22 line sensing functions. Table 46: Line Sensing Control Functions Function Register Type Mnemonic Location RXBST 0x14[3] WO CIDM 0x15[4] W RGTH 0x0E[1:0] W RGMON 0x03[3] R RGDT ...
Page 73
... Under Voltage Detector Enabled. When enabled, the ENNOM bit is temporarily set to the wide bandwidth mode if an under-voltage condition detected to allow fast reacquisition of the line. Under-Voltage Detection on Line Side Device 0 = Under Voltage condition is not detected at VPS. (Default Under Voltage condition is detected at VPS. 73M1822/73M1922 Data Sheet 73 ...
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... Data Sheet Over-Voltage Detection Control and Status ENOVD 0x15[1] WO OVDET 0x1E[5] R OVDTH 0x13[2] WO Over-Current Detection Control and Status ENOID 0x15[0] WO OIDET 0x1E[ Enable Over-Voltage Detector on Line Side Device 1 = Over Voltage Detector Enabled (not latched). Over voltage detector is enabled if ENOVD, ENFEL and ENNOM all equal 1. ...
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... Received Bit 00 Stream (RBS) and is looped back to TBS and the analog transmit channel (INTLB2). Analog Loopback. The transmit data is 00 connected to the receiver at the analog interface and received (ALB). 73M1822/73M1922 Data Sheet Ring Buffer Onchip LIC TxA TBS TxAFE ...
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... Data Sheet 13.1 Loopback Controls Table 48 describes the registers used for loopback control. Function Register Mnemonic Location TMEN 0x02[7] DTST 0x07[3:0] TEST 0x18[7:4] 76 Table 48: Loopback Controls Type Description W Test Mode Enable Used to enable the activation of the test loops controlled by the DTST bits (DIGLB1 and INTLB1). ...
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... Off-Hook Tip and Ring DC Characteristics Figure 37: Off-Hook Tip and Ring DC Characteristics Figure 38: ES 203 021-2 DC Mask with Current Limit Enabled Rev. 1.6 DCIV=00, ILM=1 DCIV=01, ILM=1 DCIV=10, ILM=1 TBR21 Not allowed Tip and Ring DC Current (mA) 73M1822/73M1922 Data Sheet Not allowed ...
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... Data Sheet 14 Australian Prohibited 12 Region Figure 39: Australian Hold State Characteristics 14.2 Receive TBR21 40 China Australia Australian not recommended Region Loop current Australia Limit USA Limit TBR21 Limit Frequency Figure 40: Return Loss DS_1x22_017 DCIV=11 Rev. 1.6 ...
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... Figure 41: 20-Pin TSSOP Package Dimensions 5 2 TOP VIEW 3.0 / 3.75 0.18 / 0.3 1.5 / 1.875 0.2 MIN. 0.35 / 0.45 0.25 0.5 BOTTOM VIEW Figure 42: 32-Pin QFN Package Dimensions Rev. 1.6 / 0.85 NOM. 0.9MAX. CHAMFERED 0. 73M1822/73M1922 Data Sheet 0.00 / 0.005 0.20 REF. SEATING PLANE SIDE VIEW 79 ...
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... Data Sheet Figure 43: 42-Pin QFN Package Dimensions 80 DS_1x22_017 Rev. 1.6 ...
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... For a complete list of worldwide sales offices http://www.teridian.com. Rev. 1.6 Order Number Packaging Mark 73M1922-IM/F 73M1912-M 73M1902-M 73M1922-IMR/F 73M1912-M 73M1902-M 73M1922-IVT/F 73M1912VT 73M1902A 73M1922-IVTR/F 73M1912VT 73M1902A 73M1822-IM/F 73M1822A-IM 73M1822-IMR/F 73M1822A-IM 73M1822/73M1922 Data Sheet Host/Line Line-Side IC Host-Side IC Line-Side IC Host-Side IC Line-Side IC Host-Side IC Line-Side IC Host-Side IC 81 ...
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... Data Sheet Revision History Revision Date Description 1.0 10/26/2007 First publication. 1.1 11/7/2007 1.1.1 4/11/2008 1.2 8/28/2008 1.3 3/23/2009 1.4 8/6/2009 1.5 10/16/2009 1.6 4/7/2010 Changed the values in Table 17. Replaced the schematics in Figure 10 and Figure 11. Updated the Bill of Materials in Table 27. ...