A2F-EVAL-KIT Actel, A2F-EVAL-KIT Datasheet - Page 10

• Manufacturer Part Number: A2F-EVAL-KIT
• Description: MCU, MPU & DSP Development Tools Smart Fusion Eval Kit
• Manufacturer: Actel

Specifications of A2F-EVAL-KIT

• Processor To Be Evaluated: A2F200M3F-FGG484
• Data Bus Width: 32 bit
• Interface Type: Ethernet, USB, SPI
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10
SmartFusion
The Intelligent Mixed-Signal FPGA
SmartFusion intelligent mixed-signal FPGAs are the only devices that integrate an FPGA, an ARM Cortex-M3 processor and programmable analog, offering full
customization, IP protection and ease-of-use. Based on Actel’s proprietary flash process, SmartFusion FPGAs are ideal for hardware and embedded designers
who need a true system-on-chip (SoC) that gives more flexibility than traditional fixed-function microcontrollers without the excessive cost of soft processor
cores on traditional FPGAs.
• Hard 100 MHz 32-bit ARM
• Multi-layer AHB communications
• 10/100 Ethernet MAC
SmartFusion Devices
Note:
1. Under definition. Subject to change.
2. These functions share I/O pins and may not all be available at the same time.
Package I/Os: MSS + FPGA I/Os
Notes:
1. Under definition. Subject to change.
2. 16 MSS I/Os are multiplexed and can be used as FPGA I/Os, if not needed for the MSS. These I/Os support Schmitt triggers and support only LVTTL and LVCMOS (1.5 / 1.8 / 2.5, 3.3 V) standards.
3. 9 MSS I/Os are primarily for 10/00 Ethernet MAC and are also multiplexed and can be used as FPGA I/Os if Ethernet MAC is not used in a design. These I/Os support Schmitt triggers and support only LVTTL and LVCMOS
SmartFusion Devices
FPGA Fabric
Microcontroller
Subsystem (MSS)
Programmable
Analog
Device
Direct Analog Input
Total Analog Input
Total Analog Output
MSS I/Os
FPGA I/Os
Total I/Os
Cortex-M3 CPU
matrix with up to 16 Gbps
throughput
(1.5 / 1.8 / 2.5, 3.3 V) standards.
2,3
System Gates
Tiles (D-flip-flops)
RAM Blocks (4,608 bits)
Flash (Kbytes)
SRAM (Kbytes)
Cortex-M3 with
Microprocessor Unit (MPU)
10/100 Ethernet MAC
External Memory Controller (EMC)
DMA
I 2 C
SPI
16550 UART
32-Bit Timer
PLL
32 KHz Low-Power Oscillator
100 MHz On-Chip RC Oscillator
Main Oscillator (1.5 MHz to 20 MHz)
ADCs (8-/10-/12-bit SAR)
DACs (12-bit sigma-delta)
Signal Conditioning Blocks (SCBs)
Comparators
Current Monitors
Temperature Monitors
Bipolar High Voltage Monitors
2
FG256
2
116
20
24
25
66
1
• Two peripherals of each type:
• Two cascadable 32-bit timers
• Up to 512 KB flash and
• External memory controller (EMC)
2
SPI, I
64 KB SRAM
A2F060
2
C and UART
2
1
Maximum
123
27
31
25
66
1
26-bit address, 16-bit data
A2F060
60,000
1,536
8 Ch
Yes
No
64
16
8
2
2
2
2
1
1
1
1
1
1
1
2
1
1
2
1
FG256
117
24
25
66
8
2
• 8-channel DMA controller
• Integrated analog-to-digital
• On-chip voltage, current and
converters (ADCs) and digital-
to-analog converters (DACs)
with 1 percent accuracy
temperature monitors
A2F200
26-bit address, 16-bit data
FG484
161
24
41
94
8
2
200,000
A2F200
4,608
8 Ch
256
Yes
Yes
64
8
2
2
2
2
1
1
1
1
2
2
4
8
4
4
8
FG256
117
• Up to ten 50 ns high-speed
• Analog compute engine (ACE)
• Up to 47 analog I/Os and
24
25
66
8
2
comparators
offloads CPU from analog
processing
169 digital GPIOs
26-bit address, 16-bit data
A2F500
500,000
A2F500
11,520
8 Ch
512
Yes
Yes
24
64
10
10
2
2
2
2
2
1
1
1
3
3
5
5
5
FG484
128
204
12
32
41
3