PEX 8680-AA50BC F PLX Technology, PEX 8680-AA50BC F Datasheet - Page 4

• Manufacturer Part Number: PEX 8680-AA50BC F
• Description: Peripheral Drivers & Components (PCIs) 80Ln/20Pt PCI Exprss Gen 2 (5 GT/s) Swtch
• Manufacturer: PLX Technology

Specifications of PEX 8680-AA50BC F

• Mounting Style: SMD/SMT
• Propagation Delay Time: 176 ns
• Package / Case: HFCBGA-1156
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Applications
Suitable for host-centric as well as peer-to-peer traffic
patterns, the PEX 8680 can be configured for a wide
variety of form factors and applications.
Host Centric Fan-out
The PEX 8680, with its symmetric or asymmetric lane
configuration capability, allows user-specific tuning to a
variety of host-centric applications. Figure 6 shows a
server design where, in a quad or multi processor
system, users can assign endpoints/slots to CPU cores to
distribute the system load. The packets directed to
different CPUs will go to different (user assigned) PEX
8680 upstream ports, allowing better queuing and load
balancing capability for higher performance.
Multi-Host Systems
In multi-host mode, the PEX 8680 can support up to six
hosts at once. By creating six virtual switches, the PEX
8680 allows six hosts to fan-out to their respective
endpoints. This reduces the number of switches required
for fan-out, saving precious board space and power. In
Figure 7, the PEX 8680 is being shared by six different
CPU cores (hosts) on three servers, with each CPU core
running its own applications (I/Os). The PEX 8680
assigns the endpoints to the appropriate host and isolates
them from the other hosts. In Figure 7, the endpoints are
assigned to the CPU core of the same color.
© PLX Technology, www.plxtech.com
Figure 6. Host Centric Dual Upstream
Figure 7. Multi-Host System
Endpoint
Endpoint
Endpoint
Endpoint
Endpoint
Endpoint
Endpoint
Endpoint
I/O
CPU
Chip
Chip
Set
Set
I/O
CPU
I/O
x4
x16
PCIe Gen1 or PCIe Gen2 slots
x8s
PEX 8680
PEX 8680
Chipset
Chipset
Chipset
Chipset
CPU
CPU
CPU
CPU
I/O
I/O
I/O
CPU
Chip
Chip
Set
Set
PEX 8680
PEX 8680
PEX 8680
PEX 8680
I/O
I/O
I/O
CPU
CPU
CPU
CPU
CPU
x8
I/O
I/O
I/O
x8
I/O
I/O
I/O
CPU
Memory
Memory
Memory
Memory
Chip
Chip
Set
Set
I/O
I/O
I/O
PEX 8680, PCI Express Gen 2 Switch, 80 Lanes, 20 Ports
CPU
I/O
I/O
I/O
x4s
Page 4 of 4
Embedded or Communications Systems
The PEX 8680’s 80 lanes can come in handy for
embedded or communications applications requiring
heavy processing and/or connectivity to multiple
endpoints. Figure 8a shows an embedded system where
the PEX 8680 is being used to fan-out to eight endpoints
using x8 and x16 links. Figure 8b shows a
communications system where the PEX 8680 is using
x16 and x8 links to fan out to I/Os and three CPUs
which have been configured as endpoints. These CPUs
will run as endpoints, conducting different processing
tasks while the host CPU (connected to the PEX 8680
via a x16 upstream link) manages them.
N+1 Fail-Over in Storage Systems
The PEX 8680’s Multi-Host feature can also be used to
develop storage array clusters where each host manages
a set of storage devices independent of others (Figure 9).
Users can designate one of the hosts as the failover-host
for all the other hosts while actively managing its own
endpoints. The failover-host will communicate with
other hosts for status/heartbeat information and execute a
failover event if/when it gets triggered.
Figure 8a. Embedded System
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PEX 8680
PEX 8680
PEX 8680
PEX 8680
I/O
I/O
I/O
I/O
I/O
I/O
Chip
Chip
CPU
CPU
CPU
CPU
Set
Set
8 Disk Chassis
8 Disk Chassis
Figure 9. N+1 Failover
I/O
I/O
I/O
I/O
I/O
I/O
x16
x4
x4
FC
FC
FC
FC
PEX 8612
PEX 8612
PEX 8612
PEX 8612
PEX 8612
PEX 8612
x4
x4
CPU
CPU
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
FC
FC
FC
FC
8 Disk Chassis
8 Disk Chassis
& x8s
x16s
x4
x4
x4
x4
x4
x4
FC
FC
FC
FC
PEX 8680
PEX 8680
PEX 8680
PEX 8680
CPU
CPU
PEX 8612
PEX 8612
PEX 8612
PEX 8612
PEX 8612
PEX 8612
8 Disk Chassis
8 Disk Chassis
FC
FC
FC
FC
x4
x4
FC
FC
FC
FC
PEX 8616
PEX 8616
PEX 8616
PEX 8616
PEX 8616
PEX 8616
x4
x4
CPU
CPU
I/O
I/O
I/O
I/O
x8
x8
x8s
8 Disk Chassis
8 Disk Chassis
I/O
I/O
I/O
I/O
Figure 8b. Comms System
FC
FC
FC
FC
x4
x4
FC
FC
FC
FC
Endpoint
Endpoint
Endpoint
Endpoint
PEX 8616
PEX 8616
PEX 8616
PEX 8616
PEX 8616
PEX 8616
x4
x4
CPU
CPU
CPU
CPU
CPU
CPU
x8
x8
Endpoint
Endpoint
Endpoint
Endpoint
PEX 8680
PEX 8680
PEX 8680
PEX 8680
FC
FC
FC
FC
CPU
CPU
CPU
CPU
Chip
Chip
x4
x4
CPU
CPU
CPU
CPU
5/14/2009, Version 1.1
Set
Set
x16s
x16
Endpoint
Endpoint
Endpoint
Endpoint
CPU
CPU
CPU
CPU