A2F500M3G-FGG484 Actel, A2F500M3G-FGG484 Datasheet - Page 22

• Manufacturer Part Number: A2F500M3G-FGG484
• Description: FPGA - Field Programmable Gate Array 500K System Gates
• Manufacturer: Actel

Specifications of A2F500M3G-FGG484

• Processor Series: A2F500
• Core: ARM Cortex M3
• Number Of Logic Blocks: 24
• Maximum Operating Frequency: 100 MHz
• Number Of Programmable I/os: 204
• Data Ram Size: 64 KB
• Delay Time: 50 ns
• Supply Voltage (max): 3.6 V
• Supply Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.5 V
• Number Of Gates: 500000
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SmartFusion DC and Switching Characteristics
Calculating Power Dissipation
Table 2-8 • Quiescent Supply Current Characteristics
Table 2-9 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings
2- 10
Modes and Power
Supplies
Time Keeping mode
Standby mode
Parameter
IDC1
IDC2
Note:
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS (JESD8-11)
3.3 V PCI
3.3 V PCI-X
Differential
LVDS
LVPECL
*On means proper voltage is applied. Refer to
Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins
Quiescent Supply Current
Power per I/O Pin
Modes
Time Keeping mode
Standby mode
On*
0 V
3.3 V
0 V
Power Supplies Configuration
VCCFPGAIOBx (V)
1.5 V Domain
1.5 V
0 V
3 mA
N/A
3.3
2.5
1.8
1.5
3.3
3.3
2.5
3.3
Table 2-3 on page 2-3
3.3 V
N/A
R e visio n 6
A2F200
3.3 V Domain
3.3 V
0 V
10 µA
1 mA
Static Power
PDC7 (mW)
N/A
0 V
2.26
5.72
for recommended operating conditions.
–
–
–
–
–
–
1.5 V Domain
N/A
0 V
TBD
N/A
Reset
Off
Dynamic Power PAC9
Enable
Enable
A2F500
(µW/MHz)
3.3 V Domain
17.55
19.21
19.21
5.97
2.88
2.33
0.82
1.16
10 µA
1 mA
Disable
Disable