LFXP3C-4TN100C Lattice, LFXP3C-4TN100C Datasheet - Page 11

• Manufacturer Part Number: LFXP3C-4TN100C
• Description: FPGA - Field Programmable Gate Array 3.1K LUTs 62 I/O 1.8/2.5/3.3V -4 Spd
• Manufacturer: Lattice

Specifications of LFXP3C-4TN100C

• Number Of Programmable I/os: 62
• Data Ram Size: 55296
• Supply Voltage (max): 3.465 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.71 V
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 2-6. Secondary Clock Sources
Clock Routing
The clock routing structure in LatticeXP devices consists of four Primary Clock lines and a Secondary Clock net-
work per quadrant. The primary clocks are generated from MUXs located in each quadrant. Figure 2-7 shows this
clock routing. The four secondary clocks are generated from MUXs located in each quadrant as shown in Figure 2-
8. Each slice derives its clock from the primary clock lines, secondary clock lines and routing as shown in Figure 2-
9.
Figure 2-7. Per Quadrant Primary Clock Selection
Clock Input
From Routing
From Routing
From Routing
From Routing
1. Smaller devices have fewer PLL related lines.
2. Dynamic clock select.
4 Primary Clocks (CLK0, CLK1, CLK2, CLK3) per Quadrant
20 Primary Clock Sources: 12 PLLs + 4 PIOs + 4 Routing
Routing
Routing
From
From
Routing
Routing
20 Secondary Clock Sources
To Quadrant Clock Selection
From
From
Clock
Clock
Input
Input
DCS
2-8
2
Routing
Routing
From
From
Routing
Routing
From
From
LatticeXP Family Data Sheet
DCS
1
2
From Routing
From Routing
From Routing
From Routing
Clock Input
Architecture