A54SX08A-TQG100 Actel, A54SX08A-TQG100 Datasheet - Page 24

• Manufacturer Part Number: A54SX08A-TQG100
• Description: FPGA - Field Programmable Gate Array 12K System Gates
• Manufacturer: Actel

Specifications of A54SX08A-TQG100

• Processor Series: A54SX08
• Core: IP Core
• Number Of Macrocells: 512
• Maximum Operating Frequency: 350 MHz
• Number Of Programmable I/os: 130
• Delay Time: 4 ns to 8.4 ns
• Supply Voltage (max): 5.25 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 2.25 V
• Number Of Gates: 8000
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-8 • AC Specifications (5 V PCI Operation)
2 -4
Symbol
I
I
I
slew
slew
Notes:
1. Refer to the V/I curves in
2. Note that this segment of the minimum current curve is drawn from the AC drive point directly to the DC drive point rather than
3. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (A
4. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any
OH(AC)
OL(AC)
CL
SX-A Family FPGAs
of that specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST#,
which are system outputs. “Switching Current High” specifications are not relevant to SERR#, INTA#, INTB#, INTC#, and INTD#,
which are open drain outputs.
toward the voltage rail (as is done in the pull-down curve). This difference is intended to allow for an optional N-channel pull-up.
and B) are provided with the respective diagrams in
design. In order to facilitate component testing, a maximum current test point is defined for each side of the output driver.
point within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter
with an unloaded output per revision 2.0 of the PCI Local Bus Specification. However, adherence to both maximum and minimum
parameters is now required (the maximum is no longer simply a guideline). Since adherence to the maximum slew rate was not
required prior to revision 2.1 of the specification, there may be components in the market for some time that have faster edge
rates; therefore, motherboard designers must bear in mind that rise and fall times faster than this specification could occur and
should ensure that signal integrity modeling accounts for this. Rise slew rate does not apply to open drain outputs.
R
F
Switching Current High
(Test Point)
Switching Current Low
(Test Point)
Low Clamp Current
Output Rise Slew Rate
Output Fall Slew Rate
Parameter
Figure 2-1 on page
2-5. Switching current characteristics for REQ# and GNT# are permitted to be one half
Output
Buffer
2.4 V to 0.4 V load
0 < V
1.4 ≤ V
3.1 < V
V
V
2.2 > V
0.71 > V
V
–5 < V
0.4 V to 2.4 V load
OUT
OUT
OUT
OUT
= 3.1
≥ 2.2
= 0.71
Figure 2-1 on page
IN
Pin
OUT
OUT
OUT
Condition
OUT
≤ –1
≤ 1.4
< 2.4
< V
3
1
> 0.55
> 0
3
v5.3
CCI
1
1, 3
1, 2
1/2 in. max.
1, 3
1
4
4
50 pF
2-5. The equation defined maximum should be met by
(–44 + (V
–25 + (V
(V
OUT
OUT
Min.
IN
–44
95
/0.023)
1
1
–
–
–
–
+ 1)/0.015
– 1.4)/0.024)
EQ 2-1 on
EQ 2-2 on
page 2-5
page 2-5
Max.
–142
206
–
–
–
–
–
5
5
Units
V/ns
V/ns
mA
mA
mA
mA
mA
mA
mA
–
–