APA300-PQ208I Actel, APA300-PQ208I Datasheet - Page 172

• Manufacturer Part Number: APA300-PQ208I
• Description: FPGA - Field Programmable Gate Array 300K System Gates
• Manufacturer: Actel

Specifications of APA300-PQ208I

• Processor Series: APA300
• Core: IP Core
• Maximum Operating Frequency: 5 MHz
• Number Of Programmable I/os: 158
• Data Ram Size: 73728
• Supply Voltage (max): 2.7 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Development Tools By Supplier: APA-Eval-Kit, APA-Eval-BRD1, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, Flashpro 4, Flashpro 3, Flashpro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 2.3 V
• Number Of Gates: 300 K
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4 -4
Previous version
v3.2
v3.1
v3.0
v2.0
ProASIC
PLUS
Flash Family FPGAs
The
Figure 2-11 • PLL Block – Top-Level View and Detailed PLL Block Diagram
Table 2-7 • Clock-Conditioning Circuitry MUX Settings
Figure 2-17 • Using the PLL for Clock Deskewing
The
Figure 2-23 • Tristate Buffer Delays
In the
The
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The datasheet was updated to include references to guidelines concerning the use of certain
ProASIC
In
Figure 2-5 • Core Cell Coordinates for the APA1000
The V
= 2.5 V ±0.2 V) Applies to Military Temperature and MIL-STD-883B Temperature Only
changed from 0.3 to –0.3.
In the
In the
and the –F maximum changed to 0.8.
The
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The
The
Table 2-2 • Array Coordinates
Figure 2-5 • Core Cell Coordinates for the APA1000
Figure 2-8 • LVPECL High and Low Threshold Values
The
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Figure 2-11 • PLL Block – Top-Level View and Detailed PLL Block Diagram
17 • Using the PLL for Clock Deskewing
The
Figure 2-22 • Multi-Port Memory Usage
The
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Applies to Military Temperature and MIL-STD-883B Temperature Only
The
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The"Input Buffer Delays" section
"Global Routing Skew" section
The"Sample Macrocell Library Listing" section
The
Changes in current version (v5.9)
Table 2-2 • Array
Introduction section
"ProASIC
"PLL Electrical Specifications" section
"Programming, Storage, and Operating Limits" section
"Recommended Design Practice for VPN/VPP" section
Table 1 • ProASICPLUS Product Profile
"Ordering Information" section
"Plastic Device Resources" section
"ProASIC
"Physical Implementation" section
"Functional Description" section
"PLL Electrical Specifications" section
"Calculating Typical Power Dissipation" section
"Nominal Supply Voltages’ section
"Tristate Buffer Delays" section
"Output Buffer Delays" section
"Pin Description" section
Table 2-24 • DC Electrical Specifications (V
IL
"Calculating Typical Power Dissipation"
"Output Buffer Delays"
"Sample Macrocell Library Listing"
Minimum in the
PLUS
I/O standards.
PLUS
PLUS
Clock Management System" section
Architecture" section
Coordinates, the Memory Rows – Bottom coordinates were changed.
Table 2-24 • DC Electrical Specifications (V
in the
was updated.
section, the OB25LPLL t
"ProASIC
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PLUS
section, the AND2 Standard maximum changed to 0.7
was updated.
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was updated.
v5.9
Clock Management System" section
section, P9 was changed to 7.5 mW.
was updated.
DDP
was updated.
was updated.
= 3.3 V ±0.3 V and V
is new.
was updated.
is new.
DHL
was updated.
is new.
Standard changed to 5.3.
was updated.
was updated.
DDP
was updated.
= 3.3 V ±0.3 V and V
was updated.
DD
through
= 2.5 V ±0.2 V)
was updated.
Figure 2-
was
DD
2-11
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