SI5320-H-BL Silicon Laboratories Inc, SI5320-H-BL Datasheet - Page 20

• Manufacturer Part Number: SI5320-H-BL
• Description: IC CLOCK MULT SONET/SDH 63-PBGA
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5320-H-BL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Si5320
2.9. Bias Generation Circuitry
The Si5320 makes use of an external resistor to set
internal bias currents. The external resistor allows
precise generation of bias currents which significantly
reduces power consumption and variation as compared
with traditional implementations that use an internal
resistor. The bias generation circuitry requires a 10 kΩ
(1%) resistor connected between REXT and GND.
2.10. Differential Input Circuitry
The Si5320 provides a differential input for the clock
input, CLKIN. This input is internally biased to a voltage
of V
differential or single-ended driver circuit. For differential
transmission lines, the termination resistor is connected
externally as shown.
2.11. Differential Output Circuitry
The Si5320 utilizes a current mode logic (CML)
architecture to drive the differential clock output,
CLKOUT.
For single-ended output operation, simply connect to
either CLKOUT+ or CLKOUT–, and leave the unused
signal unconnected.
2.12. Power Supply Connections
The Si5320 incorporates an on-chip voltage regulator.
The
20
ICM
2100
voltage
V
(see Table 2 on page 6) and may be driven by a
n
42
(μV/√Hz)
regulator
10 kHz
Figure 10. Power Supply Noise Tolerance Mask
requires
500 kHz
an
external
Rev. 2.5
compensation circuit of one resistor and one capacitor
to ensure stability over all operating conditions.
Internally, the Si5320 V
on-chip voltage regulator input, and the V
supply power to the device’s LVTTL I/O circuitry. The
V
and are also used for connection of the external
compensation circuit.
The regulator’s compensation circuit is in reality a
resistor and a capacitor in series between the V
node and ground. (See Figure 5 on page 15.) Typically,
the resistor is incorporated into the capacitor’s
equivalent series resistance (ESR). The target RC time
constant for this combination is 15 to 50 μs. The
capacitor used in the Si5320 evaluation board is a
33 μF tantalum capacitor with an ESR of 0.8 Ω. This
gives an RC time constant of 26.4 μs. The Venkel part
number, TA6R3TCR336KBR, is an example of a
capacitor that meets these specs.
To get optimal performance from the Si5320 device, the
power supply noise spectrum must comply with the plot
in Figure 10. This plot shows the power supply noise
tolerance mask for the Si5320. The customer should
provide a 3.3 V supply that does not have noise density
in excess of the amount shown in the diagram.
However, the diagram cannot be used as spur criteria
for a power supply that contains single tone noise.
DD25
pins supply power to the core DSPLL circuitry
DD33
pins are connected to the
100 Mhz
DD33
f
pins also
DD25