MSC8144VT800A Freescale Semiconductor, MSC8144VT800A Datasheet - Page 43

• Manufacturer Part Number: MSC8144VT800A
• Description: IC DSP QUAD 800MHZ 783FCBGA
• Manufacturer: Freescale Semiconductor
• Series: MSC81xx StarCorer
• Type: SC3400 Corer

Specifications of MSC8144VT800A

• Interface: Ethernet, I²C, SPI, TDM, UART, UTOPIA
• Clock Rate: 800MHz
• Non-volatile Memory: External
• On-chip Ram: 10.5MB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.00V
• Operating Temperature: 0°C ~ 90°C
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Using these waveforms, the definitions are as follows:
To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic) transmitter that has a common
mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing that goes between 2.5 V and 2.0 V. Using these values,
the peak-to-peak voltage swing of the signals TD and TD is 500 mV
and –500 mV. The peak differential voltage is 500 mV. The peak-to-peak differential voltage is 1000 mV
Note:
2.6.5.3
With the use of high speed serial links, the interconnect media will cause degradation of the signal at the receiver. Effects such
as Inter-Symbol Interference (ISI) or data dependent jitter are produced. This loss can be large enough to degrade the eye
opening at the receiver beyond what is allowed in the specification. To negate a portion of these effects, equalization can be
used. The most common equalization techniques that can be used are:
2.6.5.4
LP-Serial transmitter electrical and timing specifications are stated in the text and tables of this section. The differential return
loss, S11, of the transmitter in each case shall be better than
The reference impedance for the differential return loss measurements is 100 Ω resistive. Differential return loss includes
contributions from internal circuitry, packaging, and any external components related to the driver. The output impedance
requirement applies to all valid output levels. It is recommended that the 20–80% rise/fall time of the transmitter, as measured
at the transmitter output, have a minimum value 60 ps in each case. It is also recommended that the timing skew at the output
of an LP-Serial transmitter between the two signals comprising a differential pair not exceed 25 ps at 1.25 GB, 20 ps at 2.50
GB, and 15 ps at 3.125 GB.
Freescale Semiconductor
Output Voltage
Differential Output Voltage
Deterministic Jitter
Total Jitter
1.
2.
3.
4.
5.
6.
•
•
•
•
The transmitter output signals and the receiver input signals TD, TD, RD and RD each have a peak-to-peak voltage
(V
The differential output signal of the transmitter, V
The differential input signal of the receiver, V
The differential output signal of the transmitter and the differential input signal of the receiver each range from A – B
to –(A – B).
The peak value of the differential transmitter output signal and the differential receiver input signal is A – B.
The value of the differential transmitter output signal and the differential receiver input signal is 2 × (A – B) V
AC electrical specifications are given for transmitter and receiver. Long run and short run interfaces at three baud
rates (a total of six cases) are described. The parameters for the AC electrical specifications are guided by the XAUI
electrical interface specified in Clause 47 of IEEE™ Std 802.3ae-2002™. XAUI has similar application goals to
serial RapidIO. The goal of this standard is that electrical designs for serial RapidIO can reuse electrical designs for
XAUI, suitably modified for applications at the baud intervals and reaches described herein.
A passive high pass filter network placed at the receiver. This is often referred to as passive equalization.
The use of active circuits in the receiver. This is often referred to as adaptive equalization.
–10 dB for (baud frequency)/10 < freq(f) < 625 MHz, and
–10 dB + 10log(f/625 MHz) dB for 625 MHz ≤ freq(f) ≤ baud frequency
Characteristic
PP
) swing of A – B.
Equalization
Transmitter Specifications
Table 25. Short Run Transmitter AC Timing Specifications—1.25 GBaud
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Symbol
V
DIFFPP
V
J
J
D
O
T
–0.40
Min
500
ID
Range
, is defined as V
OD
1000
Max
2.30
0.17
0.35
, is defined as V
PP
mV
Unit
UI
UI
. The differential output signal ranges between 500 mV
V
PP
PP
PP
RD
– V
Voltage relative to COMMON of either signal
comprising a differential pair
TD
RD
– V
.
TD
.
Notes
Electrical Characteristics
PP
.
PP
.
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