XC3S1400AN-4FGG484I Xilinx Inc, XC3S1400AN-4FGG484I Datasheet - Page 54

• Manufacturer Part Number: XC3S1400AN-4FGG484I
• Description: IC FPGA SPARTAN-3AN 484FPGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S1400AN-4FGG484I

• Number Of Logic Elements/cells: 25344
• Number Of Labs/clbs: 2816
• Total Ram Bits: 589824
• Number Of I /o: 372
• Number Of Gates: 1400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 40: Switching Characteristics for the DLL (Cont’d)
Digital Frequency Synthesizer (DFS)
Table 41: Recommended Operating Conditions for the DFS
DS557 (v4.1) April 1, 2011
Product Specification
Notes:
1.
2.
3.
4.
5.
Notes:
1.
2.
3.
4.
Delay Lines
DCM_DELAY_STEP
Input Frequency Ranges
F
Input Clock Jitter Tolerance
CLKIN_CYC_JITT_FX_LF
CLKIN_CYC_JITT_FX_HF
CLKIN_PER_JITT_FX
CLKIN
The numbers in this table are based on the operating conditions set forth in
Indicates the maximum amount of output jitter that th
For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
Some jitter and duty-cycle specifications include 1% of input clock period or 0.01 UI. For example, the data sheet specifies a maximum jitter
of “±[1% of CLKIN period + 150]”. Assume the CLKIN frequency is 100 MHz. The equivalent CLKIN period is 10 ns and 1% of 10 ns is 0.1 ns
or 100 ps. According to the data sheet, the maximum jitter is ±[100 ps + 150 ps] = ±250 ps.
The typical delay step size is 23 ps.
DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) are used.
If both DFS and DLL outputs are used on the same DCM, follow the more restrictive CLKIN_FREQ_DLL specifications in
To support double the maximum effective FCLKIN limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE. This attribute divides the incoming
clock frequency by two as it enters the DCM.
CLKIN input jitter beyond these limits may cause the DCM to lose lock.
Symbol
CLKIN_FREQ_FX
Symbol
(5)
(2)
Finest delay resolution, average over all taps
(4)
Frequency for the CLKIN input
Cycle-to-cycle jitter at the
CLKIN input, based on CLKFX
output frequency
Period jitter at the CLKIN input
Description
e DCM adds to the jitter on the CLKIN input.
Description
www.xilinx.com
Spartan-3AN FPGA Family: DC and Switching Characteristics
F
F
CLKFX
CLKFX
< 150 MHz
> 150 MHz
Table 10
and
Device
All
Table
0.200
Min
–
–
–
39.
Min
15
-5
333
±300
±150
Speed Grade
Max
±1
-5
(3)
Speed Grade
Max
35
0.200
Min
–
–
–
Min
15
-4
-4
333
Table
±300
±150
Max
±1
Max
(3)
35
39.
Units
MHz
Units
ps
ps
ns
ps
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