XC6VLX365T-2FFG1759C Xilinx Inc, XC6VLX365T-2FFG1759C Datasheet - Page 10

• Manufacturer Part Number: XC6VLX365T-2FFG1759C
• Description: IC FPGA VIRTEX 6 364K 1759FFGBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™ 6 LXTr

Specifications of XC6VLX365T-2FFG1759C

• Number Of Logic Elements/cells: 364032
• Number Of Labs/clbs: 28440
• Total Ram Bits: 15335424
• Number Of I /o: 720
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1759-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Revision History
The following table shows the revision history for this document:
Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND
CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED
WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE
SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE
PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES
THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
DS150 (v2.2) January 28, 2010
Advance Product Specification
02/02/09
05/05/09
06/24/09
09/16/09
11/06/09
01/28/10
Date
Version
1.0
1.1
1.2
2.0
2.1
2.2
Initial Xilinx release.
Added the FF1156 package for both the XC6VSX315T and XC6VSX475T devices in
Updated the PCI Express design discussion on
description and clarify 8 lanes at the 5.0 Gb/s data rate. Clerical edits to
10/100/1000 Mb/s Ethernet Controller (2500 Mb/s Supported)
text.
Added ordering information and FPGA documentation sections.
Added Virtex-6 HXT family information. Updated number to 26 Mb in
Clarified distributed RAM features on
Table
Interface Blocks for PCI Express Designs
In
revised the VCO frequency minimum to 600 MHz which also revised the phase-shift timing increment.
Updated GTX transceivers operating data rate range to 6.6 Gb/s. Changed GTX PLL input reference
clock frequency divider.
Table
1. Updated compliance to the PCI Express Base Specification Revision 2.0. Updated
1, there are two Ethernet MACs in the XC6VHX255T. Under
www.xilinx.com
Description of Revisions
page
section with link to documentation.
1. Updated CLB slice number for the
page 9
to remove the LogiCORE wrapper (<100 LUT)
sections. Overall clarifications made in
Configuration
Clock Management, page
Virtex-6 Family Overview
Global Clock Lines
XC6VHX565T
section.
Table 2, page
Integrated
and
in
5,
3.
10