IDT89HP0604SZBNRG IDT, Integrated Device Technology Inc, IDT89HP0604SZBNRG Datasheet - Page 2

• Manufacturer Part Number: IDT89HP0604SZBNRG
• Description: IC SAS/SATA REPEATER 6GBPS 36QFN
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT89HP0604SZBNRG

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

P0604S Package Options
status output features in addition to I
configuration and status reporting. Note that references in this document to specific control and status output signal pins may not be available in the
36-QFN package.
P0604S Block Diagram
selections, input traffic can be muxed, demuxed, or looped back. Please, refer to modes of operation chapter for details. To facilitate buffering of
system clocks, the repeater provides 1:2 clock buffer as shown in the figure below. Powerdown (PDB) and channel enable input pins (A0EN, etc.) are
provided for easy state and channel control. Status output pins are available for monitoring critical states, such as the detection of high speed input
signals (A0SIGDET, etc.).
A2). The programming option allows the user to optimize the repeater's performance in a wide range of applications, making it an ideal solution for
most applications requiring cancellation of trace or cable attenuation and ISI jitter.
The information presented herein is subject to a Non-Disclosure Agreement and is for planning purposes only. Nothing contained in this presenta-
tion, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 89HP0604S Product Brief
The P0604S is offered with two package options as shown in Figure 2. The 100-pin BGA package provides extensive pin configuration input and
The P0604S contains four high speed channels. Each channel can routed to different outputs. Depending on user configuration via mode
Each channel’s configuration and performance can be optimized via programming pins (refer to Table 35) or via the I
®
100-BGA Package
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2
C configuration. The 36-QFN package option requires the I
Figure 2 P0604S Block Diagrams
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2
C slave on local EEPROM for optimized
36-QFN Package
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2
C interface (SCL, SDA, A0-
August 30, 2010