74VHC245D,118 NXP Semiconductors, 74VHC245D,118 Datasheet
74VHC245D,118
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74VHC245D,118 Summary of contents
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Octal bus transceiver; 3-state Rev. 01 — 25 August 2009 1. General description The 74VHC245; 74VHCT245 are high-speed Si-gate CMOS devices. The 74VHC245; 74VHCT245 are octal transceivers featuring non-inverting 3-state bus compatible outputs in both send and receive ...
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... NXP Semiconductors 4. Functional diagram DIR Fig 1. Logic symbol 74VHC_VHCT245_1 Product data sheet 74VHC245; 74VHCT245 mna174 Fig 2. IEC logic symbol Rev. 01 — 25 August 2009 Octal bus transceiver; 3-state 3EN1 3EN2 mna175 © NXP B.V. 2009. All rights reserved ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning 74VHC245 74VHCT245 DIR GND 10 Fig 3. Pin configuration SO20, TSSOP20 5.2 Pin description Table 2. Pin description Symbol Pin DIR GND 74VHC_VHCT245_1 Product data sheet 001aak059 (1) The die substrate is attached to this pad using Fig 4. Pin configuration DHVQFN20 ...
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... NXP Semiconductors Table 2. Pin description …continued Symbol Pin Functional description [1] Table 3. Function table Control OE DIR [ HIGH voltage level LOW voltage level don’t care high-impedance OFF-state. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). ...
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... NXP Semiconductors 8. Recommended operating conditions Table 5. Operating conditions Symbol Parameter 74VHC245 V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t/ V input transition rise and fall rate 74VHCT245 V supply voltage CC V input voltage I V output voltage O T ambient temperature ...
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... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions I input leakage GND current 5 OFF-state output current 5 supply current 5 input capacitance C output O capacitance 74VHCT245 V HIGH-level input voltage V LOW-level input voltage V HIGH-level ...
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... NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions 74VHC245 t propagation An; pd delay see Figure enable time Bn; en signal name DIR; see Figure disable time Bn; ...
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... NXP Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t disable time Bn; dis signal name DIR; see Figure power MHz dissipation V = GND capacitance [1] Typical values are measured at nominal supply voltage (V [2] ...
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... NXP Semiconductors OE input output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH Measurement points are given in V and V are typical voltage output levels that occur with the output load Fig 6. Enable and disable times Table 8. Measurement points Type Input V M 74VHC245 0.5V 74VHCT245 1.5 V ...
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... NXP Semiconductors negative positive Test data is given in Table Definitions test circuit Termination resistance should be equal to output impedance Load capacitance including jig and probe capacitance Load resistance Test selection switch. Fig 7. Load circuitry for measuring switching times Table 9. Test data Type Input ...
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... NXP Semiconductors 11. Package outline SO20: plastic small outline package; 20 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 2.65 mm 0.25 0.1 2.25 0.012 0.096 0.1 inches 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 12. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 13. Revision history Table 11. Revision history Document ID Release date 74VHC_VHCT245_1 20090825 ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 16. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 4 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 10.1 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 13 Revision history ...