NCP1250ASN65T1G ON Semiconductor, NCP1250ASN65T1G Datasheet - Page 17

• Manufacturer Part Number: NCP1250ASN65T1G
• Description: IC PWM CTLR OCP LATCH 6-TSOP
• Manufacturer: ON Semiconductor

Specifications of NCP1250ASN65T1G

• Output Isolation: Isolated
• Frequency Range: 61kHz ~ 71kHz
• Voltage - Input: 9.4 V ~ 28 V
• Voltage - Output: 12V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 6-TSOP (0.063", 1.60mm Width)
• Number Of Outputs: 1
• Duty Cycle (max): 84 %
• Output Current: 300 mA
• Mounting Style: SMD/SMT
• Switching Frequency: 65 KHz
• Operating Supply Voltage: 28 V
• Supply Current: 2.1 mA
• Maximum Operating Temperature: + 125 C
• Fall Time: 30 ns
• Minimum Operating Temperature: - 40 C
• Rise Time: 40 ns
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.5 V swing. If the clock operates at a 65 kHz frequency,
then the available oscillator slope corresponds to:
inductance L
a N
S
turns into a voltage ramp of the following amplitude:
of ramp compensation, then we shall inject a ramp whose
slope is 17 mV/ms. Our internal compensation being of
133 mV/ms, the divider ratio (divratio) between R
the internal 20 kW resistor is:
The series compensation resistor value is thus:
p
S
S
S
R
In the NCP1250 controller, the oscillator ramp features a
In our flyback design, let’s assume that our primary
Given a sense resistor of 330 mW, the above current ramp
If we select 50% of the downslope as the required amount
is thus given by:
ramp
p
p
sense
Figure 45. Inserting a Resistor in Series with the Current Sense Information Brings Ramp Compensation and
comp
:N
+
s
+
+ 133 kV s or 133 mV ms
ratio of 1:0.25. The off−time primary current slope
+
+ S
+ 34 kV s or 34 mV ms
V
out
V
( 1 * divratio )
R
ramp,peak
p
p
ramp
) V
L
R
is 770 mH, and the SMPS delivers 19 V with
p
sense
T
divratio +
divratio
f
sw
N
N
D
s
p
+ 103k
+
max
( 19 ) 0.8 )
+
+
133m
17m
20k
reset
latch
2.5
1 * 0.127
770m
15m
0.33
+ 0.127
0.127
0.8
Stabilizes the Converter in CCM Operation.
4
+ 103 kA s
[ 2.9 kW
+
−
from FB
setpoint
ON
comp
LEB
(eq. 10)
(eq. 12)
(eq. 13)
(eq. 14)
(eq. 11)
http://onsemi.com
and
17
20k
sense resistor to the current sense pin. We recommend
adding a small capacitor of 100 pF, from the current sense
pin to the controller ground for an improved immunity to the
noise. Please make sure both components are located very
close to the controller.
Latching Off the Controller
current set point in relationship to the line voltage, it also
offers a means to permanently latch−off the part. When the
part is latched−off, the V
around 7 V and the part stays in this state until the user cycles
the V
converter from the mains outlet. The latch detection is made
by observing the OPP pin by a comparator featuring a 3 V
reference voltage. However, for noise reasons and in
particular to avoid the leakage inductance contribution at
turn off, a 1 ms blanking delay is introduced before the
output of the OVP comparator is checked. Then, the OVP
comparator output is validated only if its high−state duration
lasts a minimum of 600 ns. Below this value, the event is
ignored. Then, a counter ensures that 4 successive OVP
events have occurred before actually latching the part. There
are several possible implementations, depending on the
needed precision and the parameters you want to control.
divider on top of the OPP one. This solution is simple and
inexpensive but requires the insertion of a diode to prevent
disturbing the OPP divider during the on time.
A resistor of the above value will then be inserted from the
The OPP pin not only allows a reduction of the peak
The first and easiest solution is the additional resistive
CS
CC
0V
2.5 V
Rcomp
down and up again, e.g. by un−plugging the
Rsense
CC
pin is internally pulled down to