LTC2942CDCB-1#PBF Linear Technology, LTC2942CDCB-1#PBF Datasheet - Page 13

• Manufacturer Part Number: LTC2942CDCB-1#PBF
• Description: IC, BATTERY FUEL GAUGE LI-ION 5.5V DFN-6
• Manufacturer: Linear Technology

Specifications of LTC2942CDCB-1#PBF

• Battery Management Function: Fuel Gauge, Charge Controller
• Battery Type: Li-Ion
• Supply Voltage Range: 2.7V To 5.5V
• Battery Ic Case Style: DFN
• No. Of Pins: 6
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

applicaTions inFormaTion
dressed is considered a slave. The LTC2942 always acts
as a slave.
Figure 3 shows an overview of the data transmission for
fast and standard mode on the I
START and STOP Conditions
When the bus is idle, both SCL and SDA must be HIGH. A
bus master signals the beginning of a transmission with a
START condition by transitioning SDA from HIGH to LOW
while SCL is HIGH. When the master has finished com-
municating with the slave, it issues a STOP condition by
transitioning SDA from LOW to HIGH while SCL is HIGH.
The bus is then free for another transmission. When
the bus is in use, it stays busy if a repeated START (Sr)
is generated instead of a STOP condition. The repeated
START (Sr) conditions are functionally identical to the
START (S).
Data Transmission
After a START condition, the I
and data transfer begins between a master and a slave.
As data is transferred over I
(eight data bits followed by an acknowledge bit), each
Figure 4. Writing FCh to the LTC2942 Control Register (B)
SDA
SCL
S
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
ADDRESS
1100100
CONDITION
START
S
W
0
A
0
ADDRESS
a6 - a0
1 - 7
REGISTER
01h
2
2
A: ACKNOWLEDGE (LOW)
A: NOT ACKNOWLEDGE (HIGH)
S: START CONDITION
P: STOP CONDITION
R: READ BIT (HIGH)
W: WRITE BIT (LOW)
C bus is considered busy
C in groups of nine bits
2
C bus.
A
0
R/W
8
DATA
FCh
Figure 3. Data Transfer Over I
ACK
A
0
9
2942 F04
P
1 - 7
b7 - b0
DATA
group takes nine SCL cycles. The transmitter releases
the SDA line during the acknowledge clock pulse and the
receiver issues an acknowledge (ACK) by pulling SDA
LOW or leaves SDA HIGH to indicate a not acknowledge
(NACK) condition. Change of data state can only happen
while SCL is LOW.
Write Protocol
The master begins a write operation with a START condi-
tion followed by the seven bit slave address 1100100
and the R/W bit set to zero, as shown in Figure 4. The
LTC2942 acknowledges this by pulling SDA LOW and
then the master sends a command byte which indicates
which internal register the master is to write. The LTC2942
acknowledges and latches the command byte into its
internal register address pointer. The master delivers the
data byte, the LTC2942 acknowledges once more and
latches the data into the desired register. The transmission
is ended when the master sends a STOP condition. If the
master continues by sending a second data byte instead
of a STOP , the LTC2942 acknowledges again, increments
its address pointer and latches the second data byte in
the following register, as shown in Figure 5.
8
2
C or SMBus
S
ACK
9
ADDRESS
1100100
Figure 5. Writing F001h to the LTC2942
Accumulated Charge Register (C, D)
1 - 7
W
0
b7 - b0
DATA
A
0
REGISTER
02h
8
A
0
ACK
9
DATA
F0h
A
0
LTC2942
CONDITION
STOP
DATA
01h
P
2942 F03
A
0
2942 F05

P
2942fa