LTC6994CS6-1#TRMPBF Linear Technology, LTC6994CS6-1#TRMPBF Datasheet - Page 8

• Manufacturer Part Number: LTC6994CS6-1#TRMPBF
• Description: IC, TIMERBLOX, SINGLE, 5.5V, 6-TSOT-23
• Manufacturer: Linear Technology

Specifications of LTC6994CS6-1#TRMPBF

• Operating Mode: Monostable
• No. Of Timers: 1
• Clock External Input: No
• Supply Voltage Range: 2.25V To 5.5V
• Digital Ic Case Style: TSOT-23
• No. Of Pins: 6
• Operating Temperature Range: 0°C To +70��C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LTC6994-1/LTC6994-2
TYPICAL PERFORMANCE CHARACTERISTICS
V
PIN FUNCTIONS
V
ply should be kept free from noise and ripple. It should be
bypassed directly to the GND pin with a 0.1µF capacitor.
DIV (Pin 2/Pin 4): Programmable Divider and Polarity
Input. The DIV pin voltage (V
into a 4-bit result (DIVCODE). V
a resistor divider between V
to ensure an accurate result. The DIV pin and resistors
should be shielded from the OUT pin or any other traces
that have fast edges. Limit the capacitance on the DIV pin
to less than 100pF so that V
of DIVCODE (POL) selects the delay functionality. For the
LTC6994-1, POL = 0 will delay the rising transition and
POL = 1 will delay the falling transition. For the LTC6994-
2, both transitions are delayed so POL = 1 can be used
to invert the output.
8
+
+
= 3.3V, R
(Pin 1/Pin 5): Supply Voltage (2.25V to 5.5V). This sup-
25
20
15
10
5
0
2
Input Propagation Delay (t
vs Supply Voltage
SET
= 200k and T
3
2V/DIV
2V/DIV
2V/DIV
SUPPLY VOLTAGE (V)
OUT
V
IN
+
Start-Up, R
(LTC6994-1)
V
+
4
= 2.5V
A
= 25°C unless otherwise noted.
+
C
(DCB/S6)
DIV
5
LOAD
SET
and GND. Use 1% resistors
PD
7.2ms
DIV
)
1ms/DIV
699412 G28
DIV
settles quickly. The MSB
= 5pF
= 800k
) is internally converted
may be generated by
6
3.0
2.5
2.0
1.5
1.0
0.5
699412 G31
0
2
Rise and Fall Time
vs Supply Voltage
3
SUPPLY VOLTAGE (V)
t
FALL
t
RISE
SET (Pin 3/Pin 3): Delay Setting Input. The voltage on the
SET pin (V
of current sourced from the SET pin (I
master oscillator frequency. The I
1.25µA to 20µA. The delayed output transition will be not
occur if I
increases above 500nA the delayed edge will transition.
A resistor connected between SET and GND is the most
accurate way to set the delay. For best performance, use
a precision metal or thin film resistor of 0.5% or better
tolerance and 50ppm/°C or better temperature coefficient.
For lower accuracy applications an inexpensive 1% thick
film resistor may be used.
Limit the capacitance on the SET pin to less than 10pF
to minimize jitter and ensure stability. Capacitance less
4
2V/DIV
2V/DIV
2V/DIV
C
OUT
5
LOAD
V
SET
IN
+
Start-Up, R
(LTC6994-2, POL = 1)
V
SET
= 5pF
699412 G29
+
= 2.5V
drops below approximately 500nA. Once I
) is regulated to 1V above GND. The amount
6
SET
500µs
100µs/DIV
50
45
40
35
30
25
20
15
10
= 50k
5
0
2
Output Resistance
vs Supply Voltage
OUTPUT SINKING CURRENT
3
SUPPLY VOLTAGE (V)
OUTPUT SOURCING CURRENT
SET
699412 G32
SET
current range is
4
) programs the
5
699412 G30
699412f
SET
6