LTC6994CS6-2#TRMPBF Linear Technology, LTC6994CS6-2#TRMPBF Datasheet - Page 10

• Manufacturer Part Number: LTC6994CS6-2#TRMPBF
• Description: IC, TIMERBLOX, SINGLE, 5.5V, 6-TSOT-23
• Manufacturer: Linear Technology

Specifications of LTC6994CS6-2#TRMPBF

• Operating Mode: Monostable
• No. Of Timers: 1
• Clock External Input: No
• Supply Voltage Range: 2.25V To 5.5V
• Digital Ic Case Style: TSOT-23
• No. Of Pins: 6
• Operating Temperature Range: 0°C To +70°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

OPERATION
LTC6994-1/LTC6994-2
The LTC6994 is built around a master oscillator with a 1µs
minimum period. The oscillator is controlled by the SET
pin current (I
conversion factor that is accurate to ±1.7% under typical
conditions.
A feedback loop maintains V
as the primary means of controlling the input-to-output
delay. The simplest way to generate I
resistor (R
V
From this equation, it is clear that V
the input-to-output delay when using a single program
resistor (R
ance and the inherent accuracy ∆t
R
between 1.25µA and 20µA).
When the input makes a transition that will be delayed
(as determined by the part version and POL bit setting),
the master oscillator is enabled to time the delay. When
the desired duration is reached, the output is allowed to
transition.
The LTC6994 also includes a programmable frequency
divider which can further divide the frequency by 1, 8, 64,
512, 4096, 2
by those same factors. The divider ratio N
resistor divider attached to the DIV pin.
With R
10
SET
SET
t
t
t
t
MASTER
MASTER
DELAY
DELAY
/R
may range from 50k to 800k (equivalent to I
SET
SET
. The master oscillator equation reduces to:
=
=
in place of V
SET
SET
=
= 1µs •
15
N
50kΩ
N
SET
DIV
50kΩ
) between SET and GND, such that I
). Error sources are limited to R
, 2
DIV
1µs
50kΩ
18
) and voltage (V
•R
•
or 2
50kΩ
R
SET
•
V
I
SET
SET
SET
V
I
SET
21
SET
SET
• 1µs
. This extends the delay duration
• 1µs
/I
SET
SET
the equation reduces to:
at 1V ±30mV, leaving I
SET
DELAY
SET
), with a 1µs/50kΩ
SET
drift will not affect
of the LTC6994.
is to connect a
DIV
is set by a
SET
SET
toler-
SET
SET
=
DIVCODE
The DIV pin connects to an internal, V
converter that determines the DIVCODE value. DIVCODE
programs two settings on the LTC6994:
1. DIVCODE determines the frequency divider setting,
2. The DIVCODE MSB is the POL bit, and configures a
V
and GND as shown in Figure 1.
Table 1 offers recommended 1% resistor values that ac-
curately produce the correct voltage division as well as the
corresponding N
resistor pairs. Other values may be used as long as:
1. The V
2. The driving impedance (R1||R2) does not exceed
DIV
N
different polarity setting on the two versions.
a. LTC6994-1: POL selects rising or falling-edge delays.
b. LTC6994-2: POL selects the output inversion.
tor tolerances and temperature effects)
500kΩ.
DIV
may be generated by a resistor divider between V+
POL = 0 will delay rising-edge transitions. POL = 1
will delay falling-edge transitions.
POL = 1 inverts the output signal.
.
Figure 1. Simple Technique for Setting DIVCODE
DIV
/V
+
ratio is accurate to ±1.5% (including resis-
DIV
and POL values for the recommended
LTC6994
699412 F01
GND
DIV
V
+
2.25V TO 5.5V
R1
R2
+
referenced 4-bit A/D
699412f