ADV7403KSTZ-140 Analog Devices Inc, ADV7403KSTZ-140 Datasheet - Page 7

• Manufacturer Part Number: ADV7403KSTZ-140
• Description: IC, VIDEO DECODER 12BIT 140MSPS LQFP-100
• Manufacturer: Analog Devices Inc

Specifications of ADV7403KSTZ-140

• Resolution (bits): 12bit
• Input Format: Analog
• Output Format: Digital
• Adc Sample Rate: 140MSPS
• No. Of Input Channels: 12
• Supply Voltage Range: 3V To 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMING CHARACTERISTICS
@ AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. Operating temperature range,
unless otherwise noted.
Table 3.
Parameter
SYSTEM CLOCK AND CRYSTAL
I
RESET FEATURE
CLOCK OUTPUTS
DATA and CONTROL OUTPUTS
1
2
3
4
5
6
7
8
2
The min/max specifications are guaranteed over this range.
Temperature range T
Guaranteed by characterization.
Maximum LLC1 frequency is 110 MHz for ADV7403BSTZ-110.
TTL input values are 0 V to 3 V, with rise/fall times ≥3 ns, measured between the 10% and 90% points.
SDP timing figures obtained using default drive strength value (0xD5) in register subaddress 0xF4.
CP timing figures obtained using max drive strength value (0xFF) in Register Subaddress 0xF4.
DDR timing specifications dependent on LLC1 output pixel clock; TLCC1/4 = 9.25 ns at LLC1 = 27 MHz.
C PORT
Crystal Nominal Frequency
Crystal Frequency Stability
Horizontal Sync Input Frequency
LLC1 Frequency Range
SCLK Frequency
SCLK Min Pulse Width High
SCLK Min Pulse Width Low
Hold Time (Start Condition)
Setup Time (Start Condition)
SDA Setup Time
SCLK and SDA Rise Time
SCLK and SDA Fall Time
Setup Time for Stop Condition
Reset Pulse Width
LLC1 Mark Space Ratio
Data Output Transition Time SDR (SDP)
Data Output Transition Time SDR (SDP)
Data Output Transition Time SDR (CP)
Data Output Transition Time SDR (CP)
Data Output Transition Time DDR (CP)
Data Output Transition Time DDR (CP)
Data Output Transition Time DDR (CP)
Data Output Transition Time DDR (CP)
DATA and CONTROL INPUTS
Input Setup Time (Digital Input Port)
Input Hold Time (Digital Input Port)
5
1, , 2 3
MIN
to T
MAX
4
: −40°C to +85°C (0°C to 70°C temperature range for ADV7403KSTZ-140).
5
7
7
7, 8
7, 8
7, 8
7, 8
6
6
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
7
8
9
11
12
13
14
15
16
17
18
19
20
:t
10
Test Conditions
Negative clock edge to start of
valid data
End of valid data to negative
clock edge
End of valid data to negative
clock edge
Negative clock edge to start of
valid data
Positive clock edge to end of
valid data
Positive clock edge to start of
valid data
Negative clock edge to end of
valid data
Negative clock edge to start of
valid data
HS_IN, VS_IN
DE_IN, data inputs
HS_IN, VS_IN
DE_IN, data inputs
Rev. SpA | Page 7 of 24
Min
14.8
12.825
0.6
1.3
0.6
0.6
100
5
45:55
−4 + TLLC1/4
0.25 + TLLC1/4
−2.95 + TLLC1/4
−0.5 + TLLC1/4
9
2.2
7
2
Typ
28.63636
0.6
Max
±50
110
140
400
300
300
55:45
3.6
2.4
2.8
0.1
ADV7403
Unit
MHz
ppm
kHz
MHz
kHz
μs
μs
μs
μs
ns
ns
ns
μs
ms
% duty
cycle
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns