INGT165BG INOVA SEMICONDUCTORS, INGT165BG Datasheet
INGT165BG
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INGT165BG Summary of contents
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Gbit/s Serial Link Transmitter and Receiver The GigaSTaR (Gigabit/s Serial Transmitter and Receiver universal high-speed point-to-point communication link. It consists of two devices, the Transmitter INGT165 and the Receiver INGR165. The INGT165 Transmitter converts parallel data up ...
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GigaSTaR LINK DESCRIPTION The GigaSTaR link is designed for reliable, high-speed, low-latency data transmission. All functions for data transfer management including the high-frequency blocks are fully integrated in the Transmitter and Receiver devices. Both devices feature a 36-bit “user-friendly” ...
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GigaSTaR INGT165 TRANSMITTER 2.1 BLOCK DIAGRAM RDCLK PDATA[35..0] Tx_SHIFTER PARITY VALID SHIFTER CTRL RESET# Figure 2: GigaSTaR Transmitter Block Diagram 12/2006 - rev. 2.1 INGT165 / INGR165 OSC EXTRC1 LOCK 1.32 GHz CLOCK GENERATOR CLOCK FRAMER HEADER MUX CTRL ...
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INGT165 TRANSMITTER PARALLEL INTERFACE The Transmitter parallel interface is designed to support different operating modes providing a maximum flexibility for the design of the application interface. PDATA[35..0] Figure 3: GigaSTaR Transmitter Parallel Interface 2.2.1 Control Signals RESET ...
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Data Burst Transfers The data burst timing provides the full data rate of 148.5 MByte/s. VALID is asserted when the first data is valid at PDATA[35.0]. With every rising edge of RDCLK the PDATA inputs are registered, serialized and ...
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Single Word Transfers Single Word Transfers are used to support lower data rates than the maximum parallel data rate of 148.5 MByte/s. VALID has to be de-asserted after the parallel read cycle signaled by one RDCLK pulse. Only one ...
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GigaSTaR INGR165 RECEIVER 3.1 BLOCK DIAGRAM OSC LOCK CLOCK GENERATOR SDATA DE_SERIALIZER SDATA# FLAGO LSYNC# Figure 6: GigaSTaR Receiver Block Diagram 12/2006 - rev. 2.1 EXTRC1 EXTRC2 1.32 GHz CLOCK DEFRAMER RES PERR# RESET# Datasheet IND165_DS INGT165 / INGR165 ...
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INGR165 RECEIVER PARALLEL INTERFACE SDATA SDATA# Figure 7: GigaSTaR Receiver Parallel Interface 3.2.1 Control Signals RESET asynchronous active low reset signal. After a power-up sequence and activation of the reference clock, RESET# has to be kept low ...
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Data Burst Transfers The data burst timing is used to support the full data rate of 148.5 MByte/s. PDATA[35..0] and PARITY are updated with each rising edge of WRCLK. RESET# LOCK LSYNC# WRCLK PDATA[35..0] PARITY PERR# Figure 8: INGR165 ...
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FLAGI / FLAGO Timing With the FLAGI / FLAGO signals a mechanism is provided to implement a sideband signalling. Each rising edge at the Transmitter’s input FLAGI toggles the FLAGO output of the Receiver. The timing diagram for the ...
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Parity Error (Reporting) Timing LSYNC # WRCLK DW1 PDATA [35..0] PERR# Figure 11: INGR165 Parity Error (reporting) timing Parameter Description t Rising edge of WRCLK marking the corrupt data word to 21 rising edge of LSYNC# t Rising edge ...
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... ABSOLUTE MAXIMUM RATINGS The absolute maximum ratings define values beyond which damage to the device may occur. Inova Semiconductors may not be held liable for any product degradation or damage caused by a violation of the absolute maximum ratings. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ...
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DC–Characteristics (under recommended operating conditions) Parameter CMOS Input High Voltage CMOS Input Low Voltage CMOS Input High Current CMOS Input Low Current EQLSEL/OSC Pin High Current EQLSEL/OSC Pin Low Current I CMOS Output High Voltage CMOS Output Low Voltage ...
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Transmitter and Receiver Timing Parameters (under recomm. operating conditions) Parameter Description t Setup time PDATA and PARITY to RDCLK rising edge 1 t VALID active to first rising RDCLK edge 2 t VALID high state 2-1 t LOCK# / ...
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INGT165 TRANSMITTER PIN DEFINITION Pin Name Pin # PDATA[0] A5 PDATA[1] B5 PDATA[2] A4 PDATA[3] B4 PDATA[4] A3 PDATA[5] B3 PDATA[6] A2 PDATA[7] B2 PDATA[8] B1 PDATA[9] C1 PDATA[10] D2 PDATA[11] E3 PDATA[12] D1 PDATA[13] E2 PDATA[14] E1 PDATA[15] F2 ...
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INGT165 TRANSMITTER PIN ASSIGNMENT (TOP VIEW PDATA PDATA PDATA [6] [4] [2] B PDATA PDATA PDATA PDATA [8] [7] [5] [3] C PDATA GND_D N. C. VCC_D [9] PDATA PDATA SYNGEN N. C. ...
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INGR165 RECEIVER PIN DEFINITION Pin Name Pin # PDATA[0] A5 PDATA[1] B5 PDATA[2] A4 PDATA[3] B4 PDATA[4] A3 PDATA[5] B3 PDATA[6] A2 PDATA[7] B2 PDATA[8] B1 PDATA[9] C1 PDATA[10] D2 PDATA[11] E3 PDATA[12] D1 PDATA[13] E2 PDATA[14] E1 PDATA[15] F2 ...
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INGR165 RECEIVER PIN ASSIGNMENT (TOP VIEW PDATA PDATA PDATA [6] [4] [2] B PDATA PDATA PDATA PDATA [8] [7] [5] [3] C PDATA GND_D N. C. VCC_D [9] PDATA PDATA VCC_D N. C. ...
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PACKAGE DIMENSIONS (12MM X 12MM PBGA) Pitch Bottom View A1 Pin Corner Top View 12/2006 - rev. 2 Figure 15: Package Dimensions Datasheet IND165_DS INGT165 / INGR165 Pitch Ball C Side View MILLIMETERS TYP. ...
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... INGSK Sample Kit (in sealed dry pack), containing 2 x INGT165B and 2 x INGR165B devices INGSKG Sample Kit (in sealed dry pack), containing 2 x INGT165BG and 2 x INGR165BG devices Table 17: Product Availability Suffix “G”: green product (RoHS-compliant) 12/2006 - rev. 2.1 INGT165 / INGR165 (I/O Current DC or transient per ...
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... DATASHEET REVISION HISTORY - Rev 2.0: new INGT165BG/INGR165BG green product version (chapter 4.6) Inova Semiconductors GmbH Grafinger Str. 26 D-81671 Munich, Germany Phone: +49 (0) Fax: +49 (0) Email: info@inova-semiconductors.de URL: http://www.inova-semiconductors.com is a registered trademark of Inova Holding GmbH registered trademark of Inova Semiconductors GmbH. ...