CS4396-KSZ Cirrus Logic Inc, CS4396-KSZ Datasheet - Page 20

• Manufacturer Part Number: CS4396-KSZ
• Description: IC, DAC, 24BIT, 192KSPS, SOIC-28
• Manufacturer: Cirrus Logic Inc

Specifications of CS4396-KSZ

• Resolution (bits): 24bit
• Sampling Rate: 192kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 4.75V To 5.25V
• Supply Current: 20mA
• Digital Ic Case Style: SOIC
• Data Interface: Serial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.0 CONTROL PORT INTERFACE
The control port is used to load all the internal settings of the CS4396. The operation of the control port
may be completely asynchronous to the audio sample rate. However, to avoid potential interference prob-
lems, the control port pins should remain static if no operation is required.
The control port has 2 modes: SPI and I
I
transition on AD0/CS after power-up, SPI mode will be selected.
6.1 SPI Mode
In SPI mode, CS is the CS4396 chip select signal, CCLK is the control port bit clock, CDIN is the input
data line from the microcontroller, CDOUT is the data output and the chip address is 0010000. The data
is clocked on the rising edge of CCLK.
Figure 5 shows the operation of the control port in SPI mode. To write to a register, bring CS low. The first
7 bits on CDIN form the chip address, and must be 0010000. The eighth bit is a read/write indicator (R/W).
The next 8 bits form the Memory Address Pointer (MAP), which is set to 01h. The next 8 bits are the data
which will be placed into the register designated by the MAP.
6.2 I
In I
with the clock to data relationship as shown in Figure 2. There is no CS pin. Pins AD0 and AD1 form the
partial chip address and should be tied to VD or DGND as required. The 7-bit address field, which is the
first byte sent to the CS4396, must be 00100(AD1)(AD0) where (AD1) and (AD0) match the setting of the
AD0 and AD1 pins. The eighth bit of the address byte is the R/W bit (high for a read, low for a write). If
the operation is a write, the next byte is the Memory Address Pointer, MAP, which selects the register to
be read or written. The MAP is then followed by the data to be written. If the operation is a read, then the
contents of the register pointed to by the MAP will be output after the chip address.
For more information on I
section.
INCR (Auto MAP Increment Enable)
20
Memory Address Pointer (MAP)
2
C operation is desired, AD0/CS should be tied to VD or DGND. If the CS4396 ever detects a high to low
2
INCR
C mode, SDA is a bi-directional data line. Data is clocked into and out of the part by the clock, SCL,
2
7
0
C Mode
Reserved
1 - Enabled
Default = ‘0’
0 - Disabled
6
0
2
C, please see “The I
Reserved
5
0
2
C, with the CS4396 operating as a slave device in both modes. If
Reserved
MAP0-2 (Memory Address Pointer)
Default = ‘001’
4
0
2
C-Bus Specification: Version 2.0”, listed in the References
Reserved
3
0
MAP2
2
0
MAP1
1
0
CS4396
DS288PP1
MAP0
0
1