ISL34321INZ Intersil, ISL34321INZ Datasheet

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... CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 1-888-468-3774 Intersil (and design registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2009, 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners. (see page 12) FN6827 “ ...

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Block Diagram SCL SDA RAM 3 V/H/DE TDM RGB 16 VIDEO_TX (HI) PCLK_IN (REF_CLK WHEN VIDEO_TX IS LO) PCLK_OUT Pin Configuration GND_IO VDD_IO PCLK_OP RGBA0 RGBA1 RGBA2 RGBA3 RGBA4 RGBA5 RGBA6 RGBA7 GND_IO 2 ISL34321 MUX 8b/10b ...

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Pin Descriptions PIN NUMBER PIN NAME 47, 46 RGBA7, RGBA6 45, 44 RGBA5, RGBA4 43, 42 RGBA3, RGBA2 41, 40 RGBA1, RGBA0 9, 8 RGBC7, RGBC6 7, 6 RGBC5, RGBC4 5, 4 RGBC3, RGBC2 3, 2 RGBC1, RGBC0 16 HSYNC ...

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... PART NUMBER (Notes PART MARKING ISL34321INZ ISL34321 INZ 3. Add “-T13” suffix for tape and reel. Please refer to 4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations) ...

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... Thermal Resistance (Typical) EPTQFP (Notes Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . 327mW Maximum Junction Temperature Maximum Storage Temperature Range . . . -65°C to +150°C Operating Temperature Range . . . . . . . . . . -40°C to +85°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp = +25°C, Ref_Res = 3.16kΩ, High-speed A SYMBOL CONDITIONS PCLK_IN = 45MHz (Note 8) ...

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Electrical Specifications Unless otherwise indicated, all data is for: VDD_CDR = VDD_CR = 1.8V, VDD_IO = 3.3V VDD_TX = VDD_P = VDD_AN = 3.3V, T AC-coupling capacitor = 27nF. (Continued) PARAMETER Output Rise and Fall Times SERIALIZER PARALLEL INTERFACE PCLK_IN ...

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Electrical Specifications Unless otherwise indicated, all data is for: VDD_CDR = VDD_CR = 1.8V, VDD_IO = 3.3V VDD_TX = VDD_P = VDD_AN = 3.3V, T AC-coupling capacitor = 27nF. (Continued) PARAMETER HIGH SPEED RECEIVER HS Differential Input Voltage HS Generated ...

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Diagrams VOD VIDEO_TX = 1 PCLK_IN T IS RGB[A:C][7:0] HSYNC VSYNC DATAEN FIGURE 2. PARALLEL VIDEO INPUT TIMING [PCLK_IN ACTIVE LOW, HSYNC/VSYNC ACTIVE HIGH] 8 ISL34321 TR FIGURE 1. VOD vs. TXCN SETTING 1 VALID DATA VALID ...

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VIDEO_TX = 0 PCLK_OUT T DV RGB[A:C][7:0] HSYNC VSYNC DATAEN FIGURE 3. PARALLEL VIDEO OUTPUT TIMING [PCLK_OUT ACTIVE LOW, HSYNC/VSYNC ACTIVE HIGH] Applications Detailed Description and Operation A pair of ISL34321 SERDES transports 16-bit parallel video for the ISL34321 along ...

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Power Supply Sequencing The 3.3V supply must be higher than the 1.8V supply at all times, including during power-up and power-down. To meet this requirement, the 3.3V supply must be powered up before the 1.8V supply. For the deserializer, REF_CLK ...

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Master Mode This is a mode activated by strapping the MASTER pin to a ‘1’ on the ISL34321 on the remote side of the controller. This is a virtual extension of the I across the link that allows the local ...

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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries ...

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Package Outline Drawing Q48.7x7B 48 LEAD THIN PLASTIC QUAD FLATPACK EXPOSED PAD PACKAGE Rev 2, 7/10 9.0±0. 0.50 TOP VIEW 11/13° 1.20 MAX 0.08 0.17/0.27 7 0.09/0.20 0.09/0.16 0.17/0.23 (10.00) (10.00) (4.00) TYPICAL RECOMMENDED LAND PATTERN ...