DSPIC30F4011-20E/P Microchip Technology, DSPIC30F4011-20E/P Datasheet - Page 5

• Manufacturer Part Number: DSPIC30F4011-20E/P
• Description: IC, DSC, 16BIT, 48KB, 40MHZ, 5.5V, DIP40
• Manufacturer: Microchip Technology
• Series: DsPIC30Fr

Specifications of DSPIC30F4011-20E/P

• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 30
• Flash Memory Size: 48KB
• Supply Voltage Range: 2.5V To 5.5V
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 48KB (16K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC30F003 - MODULE SOCKET DSPIC30F 40DIPACICE0206 - ADAPTER MPLABICE 40P 600 MIL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: DSPIC30F4011-20EP

Register 35-2:
© 2008 Microchip Technology Inc.
Upper Byte:
bit 15
bit 15-13 Unimplemented: Read as ‘0’
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4-2
Note 1: The SMP bit must be set only after setting the MSTEN bit. The SMP bit remains cleared if MSTEN = 0.
U-0
—
2: The CKE bit is not used in the Framed SPI modes. The user application should program this bit to ‘0’ for
DISSCK: Disable SCK1 Pin bit (SPI Master modes only)
1 = Internal SPI clock is disabled; pin functions as I/O
0 = Internal SPI clock is enabled
DISSDO: Disable SDO1 Pin bit
1 = SDO1 pin is not used by the module; pin functions as I/O
0 = SDO1 pin is controlled by the module
MODE16: Word/Byte Communication Select bit
1 = Communication is word-wide (16 bits)
0 = Communication is byte-wide (8 bits)
SMP: SPI1 Data Input Sample Phase bit
Master mode:
1 = Input data is sampled at the end of data output time
0 = Input data is sampled at the middle of data output time
Slave mode:
SMP must be cleared when SPI1 is used in Slave mode
CKE: SPI1 Clock Edge Select bit
1 = Serial output data changes on transition from active clock state to Idle clock state (see bit 6)
0 = Serial output data changes on transition from Idle clock state to active clock state (see bit 6)
SSEN: Slave Select Enable bit (Slave mode)
1 = SS1 pin is used for Slave mode
0 = SS1 pin is not used by module; pin is controlled by port function
CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level; active state is a low level
0 = Idle state for clock is a low level; active state is a high level
MSTEN: Master Mode Enable bit
1 = Master mode
0 = Slave mode
SPRE<2:0>: Secondary Prescale bits (Master mode)
111 = Secondary prescale 1:1
110 = Secondary prescale 2:1
•
•
•
000 = Secondary prescale 8:1
the Framed SPI modes (FRMEN = 1).
U-0
—
SPI1CON1: SPI1 Control Register 1
Lower Byte:
bit 7
Section 35. Serial Peripheral Interface (SPI) (Part II)
R/W-0
SSEN
U-0
—
R/W-0
CKP
DISSCK
R/W-0
(2)
MSTEN
R/W-0
(1)
DISSDO
R/W-0
R/W-0
MODE16
R/W-0
SPRE<2:0>
R/W-0
SMP
R/W-0
(1)
R/W-0
CKE
R/W-0
(2)
bit 8
R/W-0
DS70272B-page 35-5
PPRE<1:0>
R/W-0
bit 0
35