DSPIC30F4012-20I/SO Microchip Technology, DSPIC30F4012-20I/SO Datasheet - Page 111

• Manufacturer Part Number: DSPIC30F4012-20I/SO
• Description: IC, DSC, 16BIT, 48KB 20MHZ, 5.5V, SOIC28
• Manufacturer: Microchip Technology
• Series: DsPIC30Fr

Specifications of DSPIC30F4012-20I/SO

• Core Frequency: 20MHz
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 20
• Flash Memory Size: 48KB
• Supply Voltage Range: 2.5V To 5.5V
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 48KB (16K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Package: 28SOIC W
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 20
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 6-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F401220ISO

16.3
The SS1 pin allows a Synchronous Slave mode. The
SPI must be configured in SPI Slave mode, with SS1
pin control enabled (SSEN = 1). When the SS1 pin is
low, transmission and reception are enabled and the
SDO1 pin is driven. When SS1 pin goes high, the
SDO1 pin is no longer driven. Also, the SPI module is
resynchronized and all counters/control circuitry are
reset. Therefore, when the SS1 pin is asserted low
again, transmission/reception will begin at the MSb,
even if SS1 had been deasserted in the middle of a
transmit/receive.
© 2010 Microchip Technology Inc.
Slave Select Synchronization
16.4
During Sleep mode, the SPI module is shut down. If
the CPU enters Sleep mode while an SPI transaction
is in progress, then the transmission and reception is
aborted.
The transmitter and receiver will stop in Sleep mode.
However, register contents are not affected by
entering or exiting Sleep mode.
16.5
When the device enters Idle mode, all clock sources
remain functional. The SPISIDL bit (SPI1STAT<13>)
selects if the SPI module will stop or continue on Idle.
If SPISIDL = 0, the module will continue to operate
when the CPU enters Idle mode. If SPISIDL = 1, the
module will stop when the CPU enters Idle mode.
dsPIC30F4011/4012
SPI Operation During CPU Sleep
Mode
SPI Operation During CPU Idle
Mode
DS70135G-page 111