DSP56321TFC220D Freescale Semiconductor, DSP56321TFC220D Datasheet
DSP56321TFC220D
Specifications of DSP56321TFC220D
Related parts for DSP56321TFC220D
DSP56321TFC220D Summary of contents
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... Freescale Semiconductor, Inc. Technical Data Advance Information DSP56321T/D Rev. 2, 10/2002 24-Bit Digital Signal Processor 3 SCI The DSP56321T is a member of the DSP56300 Digital Address Generation Signal Processor (DSP) Unit Six Channel family intended for DMA Unit applications requiring a large amount of Bootstrap ROM on-device memory ...
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... Means that a high true (active high) signal is low or that a low true (active low) signal is high Examples: Signal/Symbol PIN PIN PIN PIN Note: Values for and Freescale Semiconductor, Inc. Logic State True False True False are defined by individual product specifications. OH For More Information On This Product, Go to: www.freescale.com Signal State Voltage Asserted V /V ...
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... Freescale Semiconductor, Inc. DSP56321T Features High-Performance DSP56300 Core • 220/240 million multiply-accumulates per second (MMACS) (440/480 MMACS using the EFCOP in filtering applications) with a 220/240 MHz clock at 1.6 V core and 3.3 V I/O and a junction temperature range of 0–85°C • Object code compatible with the DSP56000 core with highly parallel instruction set • ...
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... Wait and Stop low-power standby modes • Fully static design specified to operate down (dc) • Optimized power management circuitry (instruction-dependent, peripheral-dependent, and mode-dependent) Packaging The DSP56321T is available in a 196-pin flip-chip plastic ball grid array (FC-PBGA) package. iv Freescale Semiconductor, Inc. Instruction X Data RAM Y Data RAM Cache Size Size* 0 ...
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... Freescale Semiconductor, Inc. Target Applications DSP56321/DSP56321T applications require high performance, low power, small packaging, and a large amount of on-chip memory. The EFCOP can accelerate general filtering applications. Examples include: • Wireless and wireline infrastructure applications • Multi-channel wireless local loop systems • Security encryption systems • ...
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... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. Chapter 1 Signal/ Connection Descriptions 1.1 Signal Groupings The DSP56321T input and output signals are organized into functional groups as shown in Table 1-1. Figure 1-1 diagrams the DSP56321T signals by functional group. The remainder of this chapter describes the signal pins in each functional group. ...
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... The ESSI0, ESSI1, and SCI signals are multiplexed with the Port C GPIO signals (PC[0–5]), Port D GPIO signals (PD[0–5]), and Port E GPIO signals (PE[0–2]), respectively. 3. TIO[0–2] can be configured as GPIO signals. 1-2 Freescale Semiconductor, Inc. DSP56321T Interrupt/ Power Inputs: Mode Control ...
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... Freescale Semiconductor, Inc. 1.2 Power Power Name V CCQL V CCQH V CCA V CCD V CCC V CCH V CCS Note: The user must provide adequate external decoupling capacitors for all power connections. 1.3 Ground Ground Name GND Note: The user must provide adequate external decoupling capacitors for all GND connections. ...
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... Port A signals: RD 1.5.1 External Address Bus Signal Name A[0–17] 1.5.2 External Data Bus Signal Name D[0–23] Input/ Output 1-4 Freescale Semiconductor, Inc CAS Table 1-5. External Address Bus Signals State During Type Reset, Stop, or ...
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... Freescale Semiconductor, Inc. 1.5.3 External Bus Control Signal Name AA[0–3] Output RD Output WR Output TA Input BR Output Table 1-7. External Bus Control Signals State During Type Reset, Stop, or Wait Tri-stated Address Attribute—When defined as AA, these signals can be used as chip selects or additional address lines. The default use defines a priority scheme under which only one AA signal can be asserted at a time ...
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... Signal Name BG Input BB Input/ Output 1-6 Freescale Semiconductor, Inc. Table 1-7. External Bus Control Signals (Continued) State During Type Reset, Stop, or Wait Ignored Input Bus Grant—Asserted by an external bus arbitration circuit when the DSP56321T becomes the next bus master. When BG is asserted, the DSP56321T must wait until BB is deasserted before taking bus mastership ...
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... Freescale Semiconductor, Inc. 1.6 Interrupt and Mode Control The interrupt and mode control signals select the chip operating mode as it comes out of hardware reset. After RESET Signal Name MODA IRQA MODB IRQB MODC IRQC MODD IRQD RESET PINIT NMI is deasserted, these inputs are hardware interrupt request lines. ...
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... H[0–7] HAD[0–7] PB[0–7] 1-8 Freescale Semiconductor, Inc. Table 1-9. Host Port Usage Considerations When reading the receive byte registers, Receive register High (RXH), Receive register Middle (RXM), or Receive register Low (RXL), the host interface programmer should use interrupts or poll the Receive register Data Full (RXDF) flag that indicates data is available ...
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... Freescale Semiconductor, Inc. Table 1-10. Host Interface (Continued) State During Signal Name Type 1,2 Reset HA0 Input Ignored Input HAS/HAS Input PB8 Input or Output HA1 Input Ignored Input HA8 Input PB9 Input or Output HA2 Input Ignored Input HA9 Input PB10 Input or Output ...
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... HRW HRD/HRD PB11 HDS/HDS HWR/HWR PB12 HREQ/HREQ HTRQ/HTRQ PB14 1-10 Freescale Semiconductor, Inc. Table 1-10. Host Interface (Continued) State During Type 1,2 Reset Input Ignored Input Host Read/Write—When the HI08 is programmed to interface with a single-data-strobe host bus and the HI function is selected, this signal is the Host Read/Write (HRW) input ...
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... Freescale Semiconductor, Inc. Table 1-10. Host Interface (Continued) State During Signal Name Type 1,2 Reset HACK/HACK Input Ignored Input HRRQ/HRRQ Output PB15 Input or Output Notes the Stop state, the signal maintains the last state as follows: • If the last state is input, the signal is an ignored input. ...
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... SC00 PC0 SC01 PC1 SC02 PC2 SCK0 PC3 1-12 Freescale Semiconductor, Inc. Table 1-11. Enhanced Synchronous Serial Interface 0 State During Type 1,2 Reset Input or Output Ignored Input Serial Control 0—For asynchronous mode, this signal is used for the receive clock I/O (Schmitt-trigger input). For synchronous mode, this signal is used either for transmitter 1 output or for serial I/O flag 0 ...
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... Freescale Semiconductor, Inc. Signal Name SRD0 PC4 STD0 PC5 Notes 1.9 Enhanced Synchronous Serial Interface 1 (ESSI1) Signal Name SC10 PD0 SC11 PD1 Enhanced Synchronous Serial Interface 1 (ESSI1) Table 1-11. Enhanced Synchronous Serial Interface 0 (Continued) State During Type 1,2 Reset Input Ignored Input Serial Receive Data— ...
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... PD3 SRD1 PD4 STD1 PD5 Notes 1-14 Freescale Semiconductor, Inc. Table 1-12. Enhanced Serial Synchronous Interface 1 (Continued) State During Type 1,2 Reset Input/Output Ignored Input Serial Control Signal 2—The frame sync for both the transmitter and receiver in synchronous mode and for the transmitter only in asynchronous mode ...
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... Freescale Semiconductor, Inc. 1.10 Serial Communication Interface (SCI) The SCI provides a full duplex port for serial communication with other DSPs, microprocessors, or peripherals such as modems. Signal Name RXD PE0 TXD PE1 SCLK PE2 Notes Table 1-13. Serial Communication Interface State During Type ...
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... Signal Name TIO0 TIO1 TIO2 Notes 1-16 Freescale Semiconductor, Inc. Table 1-14. Triple Timer Signals State During Type 1,2 Reset Input or Output Ignored Input Timer 0 Schmitt-Trigger Input/Output— When Timer 0 functions as an external event counter or in measurement mode, TIO0 is used as input ...
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... Freescale Semiconductor, Inc. 1.12 JTAG and OnCE Interface The DSP56300 family and in particular the DSP56321T support circuit-board test strategies based on the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture, the industry standard developed under the sponsorship of the Test Technology Committee of IEEE and the JTAG. ...
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... JTAG and OnCE Interface 1-18 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. Chapter 2 Specifications 2.1 Introduction The DSP56321T is fabricated in high-density CMOS with Transistor-Transistor Logic (TTL) compatible inputs and outputs. Note: The DSP56321T specifications are preliminary and are from design simulations, and may not be fully tested or guaranteed. Finalized specifications will be published after full characterization and device qualifications are complete ...
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... Junction-to-ambient, natural convection, four-layer board (2s2p) Junction-to-ambient, @200 ft/min air flow, single-layer board (1s) Junction-to-ambient, @200 ft/min air flow, four-layer board (2s2p) Junction-to-board Junction-to-case thermal resistance Notes 2-2 Freescale Semiconductor, Inc. Table 2-1. Absolute Maximum Ratings 1 Rating Symbol 3 V CCQL 3 V CCQH V ...
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... Freescale Semiconductor, Inc. 2.4 DC Electrical Characteristics Supply voltage • Core (V CCQL • I/O (V CCQH Input high voltage • D[0–23], BG, BB, TA • MOD/IRQ JTAG/ESSI/SCI/Timer/HI08 pins 9 • EXTAL Input low voltage • D[0–23], BG, BB, TA, MOD • All JTAG/ESSI/SCI/Timer/HI08 pins 9 • EXTAL ...
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... EXTAL and XTAL; an example is shown in Figure 2-1 EXTAL C Fundamental Frequency Crystal Oscillator 2-4 Freescale Semiconductor, Inc. minimum of 2.4 V for all pins except EXTAL, which is tested using the input levels IH Table 2-4. Internal Clocks Symbol f T ...
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... Freescale Semiconductor, Inc. Table 2-5. External Clock Operation No. Characteristics 1 Frequency of EXTAL (EXTAL Pin Frequency) • With DPLL disabled 2 • With DPLL enabled 3 2 EXTAL input high • With DPLL disabled (46.7%–53.3% duty cycle • With DPLL enabled (42.5%–57.5% duty cycle ...
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... DPLL lock procedure duration is specified for the case when an external clock source is supplied to the EXTAL pin. Parameters will be refined after silicon characterization. 5. Frequency-only Lock Mode or non-integer MF, after partial reset. 6. Frequency and Phase Lock Mode, integer MF, after full reset. 2-6 Freescale Semiconductor, Inc. Table 2-6. CLKGEN and DPLL Characteristics Characteristics For More Information On This Product, Go to: www ...
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... Freescale Semiconductor, Inc. 2.5.4 Reset, Stop, Mode Select, and Interrupt Timing No. Characteristics 8 Delay from RESET assertion to all pins at 3 reset value 9 Required RESET duration Power on, external clock generator, DPLL disabled Power on, external clock generator, DPLL enabled Power on, internal oscillator During STOP, XTAL disabled ...
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... When fast interrupts are used and IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply to prevent multiple interrupt service. To avoid these timing restrictions, the deasserted Edge-triggered mode is recommended when fast interrupts are used. Long interrupts are recommended for Level-sensitive mode. 2-8 Freescale Semiconductor, Inc. Expression 2, 3 DPLT + (128K DPLT + (23.75 ± 0.5) (8 ...
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... Freescale Semiconductor, Inc. Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing No. Characteristics 2. This timing depends on several settings: For DPLL disable, using internal oscillator (DPLL Control Register (PCTL) Bit and oscillator disabled during Stop (PCTL Bit 1 = 0), a stabilization delay is required to assure that the oscillator is stable before programs are executed ...
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... AC Electrical Characteristics IRQA, IRQB, IRQC, IRQD, IRQA, IRQB, IRQC, IRQD, IRQA, IRQB, IRQC, IRQD, NMI IRQA, IRQB, IRQC, IRQD, NMI 2-10 Freescale Semiconductor, Inc. A[0–17 NMI a) First Interrupt Instruction Execution General Purpose I/O 18 NMI b) General-Purpose I/O Figure 2-4. External Fast Interrupt Timing Figure 2-5 ...
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... Freescale Semiconductor, Inc. RESET MODA, MODB, MODC, MODD, PINIT Figure 2-6. Operating Mode Select Timing 24 IRQA A[0–17] Figure 2-7. Recovery from Stop State Using IRQA IRQA A[0–17] Figure 2-8. Recovery from Stop State Using IRQA Interrupt Service A[0–17] ...
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... Data valid to WR deassertion (data setup time) 109 Data hold time from WR deassertion 110 WR assertion to data active 111 WR deassertion to data high impedance 112 Previous RD deassertion to data active (write) 113 RD deassertion time 2-12 Freescale Semiconductor, Inc. Table 2-8. SRAM Timing Symbol Expression ( ( 0. ...
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... Freescale Semiconductor, Inc. Table 2-8. SRAM Timing (Continued) No. Characteristics 4 114 WR deassertion time 115 Address valid to RD assertion 116 RD assertion pulse width 117 RD deassertion to address not valid 118 TA setup before deassertion 119 TA hold after deassertion Notes the number of wait states specified in the BCR. The value is given for the minimum for a given category. (For example, for a category of [3 otherwise ...
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... To guarantee timings 250 and 251 recommended that you assert non-overlapping BG inputs to different DSP56300 devices (on the same bus), as shown in Figure 2-12, where BG1 is the BG signal for one DSP56300 device while BG2 is the BG signal for a second DSP56300 device. 2-14 Freescale Semiconductor, Inc. 107 101 114 Figure 2-11 ...
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... Freescale Semiconductor, Inc. BG1 BB BG2 Figure 2-12. Asynchronous Bus Arbitration Timing The asynchronous bus arbitration is enabled by internal synchronization circuits on These synchronization circuits add delay from the external signal until it is exposed to internal logic result of this delay, a DSP56300 part may assume mastership and assert deasserted ...
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... Address (HAD[0–7]) hold time after HAS deassertion (HMUX=1) 336 HA[8–10] (HMUX=1), HA[0–2] (HMUX=0), HR/W setup time before data strobe assertion • Read • Write 2-16 Freescale Semiconductor, Inc. Table 2-10. Host Interface Timings 10 Characteristic after “Last Data Register” 8,11 6 ...
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... Freescale Semiconductor, Inc. Table 2-10. Host Interface Timings No. Characteristic 337 HA[8–10] (HMUX=1), HA[0–2] (HMUX=0), HR/W hold time 4 after data strobe deassertion 338 Delay from read data strobe deassertion to host request assertion for “Last Data Register” read 339 Delay from write data strobe deassertion to host request assertion for “ ...
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... AC Electrical Characteristics Figure 2-14. Read Timing Diagram, Non-Multiplexed Bus, Single Data Strobe Figure 2-15. Read Timing Diagram, Non-Multiplexed Bus, Double Data Strobe 2-18 Freescale Semiconductor, Inc. HA[2–0] HCS 336 HRW HDS 326 H[7–0] 341 HREQ (single host request) HRRQ (double host request) HA[2– ...
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... Freescale Semiconductor, Inc. HA[2–0] HCS 336 HRW HDS H[7–0] HREQ (single host request) HTRQ (double host request) Figure 2-16. Write Timing Diagram, Non-Multiplexed Bus, Single Data Strobe HA[2–0] HCS HWR H[7–0] HREQ (single host request) HTRQ (double host request) Figure 2-17 ...
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... AC Electrical Characteristics 2-20 Freescale Semiconductor, Inc. , HA[10–8] 322 HAS 336 HRW HDS 334 HAD[7–0] Address HREQ (single host request) HRRQ (double host request) Figure 2-18. Read Timing Diagram, Multiplexed Bus, Single Data Strobe HA[10–8] 322 HAS HRD 334 HAD[7– ...
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... Freescale Semiconductor, Inc. HA[10–8] 322 HAS 336 HRW HDS 334 335 HAD[7–0] Address HREQ (single host request) HTRQ (double host request) Figure 2-20. Write Timing Diagram, Multiplexed Bus, Single Data Strobe , HA[10–8] 322 HAS HWR 334 335 HAD[7–0] ...
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... In the timing diagrams below, the SCLK is drawn using the clock falling edge as a the first reference. Clock polarity is programmable in the SCI Control Register (SCR). Refer to the DSP56321 Reference Manual for details. 2-22 Freescale Semiconductor, Inc. Table 2-11. SCI Timings 1 Symbol ...
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... Freescale Semiconductor, Inc. 401 SCLK (Output) 403 Data Valid TXD 405 Data RXD Valid a) Internal Clock 401 SCLK (Input) 407 TXD 409 RXD b) External Clock Figure 2-22. SCI Synchronous Mode Timing 412 1X SCLK (Output) 414 TXD Figure 2-23. SCI Asynchronous Mode Timing For More Information On This Product, Go to: www ...
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... TXC rising edge to FST out (bit-length) low 448 TXC rising edge to FST out (word-length-relative) 2 high 449 TXC rising edge to FST out (word-length-relative) 2 low 2-24 Freescale Semiconductor, Inc. Table 2-12. ESSI Timings 4, 6 Symbol T ECCX T ECCI 2 For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. Table 2-12. ESSI Timings (Continued No. Characteristics 450 TXC rising edge to FST out (word-length) high 451 TXC rising edge to FST out (word-length) low 452 TXC rising edge to data out enable from high impedance 453 TXC rising edge to Transmitter #0 drive enable ...
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... AC Electrical Characteristics FST (Bit) FST (Word) Data Out Transmitter FST (Bit) In FST (Word) Flags Out Note: 2-26 Freescale Semiconductor, Inc. 430 431 TXC (Input/ Output) 446 447 Out 450 Out 454 452 459 #0 Drive Enable 457 458 In In Network mode, output flag transitions can occur at the start of each time slot within the frame. In Normal mode, the output flag state is asserted for the entire frame period ...
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... Freescale Semiconductor, Inc. 430 431 RXC 432 (Input/ Output) 433 434 FSR (Bit) Out 437 FSR (Word) Out Data In 441 FSR (Bit) In 442 FSR (Word) In Flags In Figure 2-25. ESSI Receiver Timing For More Information On This Product, Go to: www.freescale.com AC Electrical Characteristics 440 ...
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... In the timing diagrams below, TIO is drawn using the rising edge as the reference. TIO polarity is programmable in the Timer Control/Status Register (TCSR). Refer to the DSP56321 Reference Manual for details. TIO TIO (Input) Address 2-28 Freescale Semiconductor, Inc. Table 2-13. Timer Timings Characteristics Expression 2 T ...
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... Freescale Semiconductor, Inc. 2.5.10 CONSIDERATIONS FOR GPIO USE The following considerations can be helpful when GPIO is used. 2.5.10.1 GPIO as Output • The time from fetch of the instruction that changes the GPIO pin to the actual change is seven core clock cycles, if the instruction pipeline delays. ...
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... TRST assert time 513 TRST setup time to TCK low Notes TCK (Input) 2-30 Freescale Semiconductor, Inc. Table 2-14. JTAG Timing Characteristics V = 3 1 CCQH CCQL All timings apply to OnCE module data transfers because it uses the JTAG port as an interface. ...
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... Freescale Semiconductor, Inc. TCK V (Input) IL Data Inputs 506 Data Outputs 507 Data Outputs 506 Data Outputs Figure 2-29. Boundary Scan (JTAG) Timing Diagram TCK V (Input) IL TDI TMS (Input) 510 TDO (Output) 511 TDO (Output) 510 TDO (Output) Figure 2-30. Test Access Port Timing Diagram ...
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... DE assertion time in order to enter Debug mode 515 Response time when DSP56321T is executing NOP instructions from internal memory 516 Debug acknowledge assertion time Note: V CCQH DE 2-32 Freescale Semiconductor, Inc. Table 2-15. OnCE Module Timing Characteristics = 3 1 CCQL 514 515 Figure 2-32. OnCE—Debug Request For More Information On This Product, Go to: www ...
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... Freescale Semiconductor, Inc. Chapter 3 Packaging 3.1 Pin-Out and Package Information This section includes diagrams of the signals described in 196-pin Flip Chip-Plastic Ball Grid Array (FC-PBGA) package. DSP56321T are allocated for the package. The Chapter 1 For More Information On This Product, Go to: www.freescale.com package pin-outs and tables showing how the ...
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... RXD SC10 G SCK1 SCLK CCQH CCQL HACK J HRW K HREQ V CCS HCS TIO1 L M HA1 HA2 3-2 Freescale Semiconductor, Inc. Top View TMS TDO IRQB D23 V CCD TRST IRQD TDI D21 D20 IRQA IRQC TCK D22 V CCQL DE GND GND GND GND GND ...
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... Freescale Semiconductor, Inc D11 D14 D10 D13 D12 CCD GND GND CCD D0 A16 A17 GND GND A15 A14 V GND GND CCQH A12 V A13 GND GND CCQL A11 A10 V GND GND CCA GND GND V GND GND A6 A5 CCA GND GND CCA RD WR ...
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... SRD1 or PD4 B2 SC12 or PD2 B3 TDI B4 TRST B5 MODD/IRQD B6 D21 B7 D20 B8 D17 B9 D15 B10 D13 B11 D10 3-4 Freescale Semiconductor, Inc. Table 3-1. Signal List by Ball Number Ball Signal Name Signal Name No. B12 D8 B13 D5 B14 NC C1 SC02 or PC2 C2 STD1 or PD5 C3 TCK C4 MODA/IRQA C5 MODC/IRQC ...
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... Freescale Semiconductor, Inc. Table 3-1. Signal List by Ball Number (Continued) Ball Ball Signal Name No. No. F6 GND H3 F7 GND H4 F8 GND H5 F9 GND H6 F10 GND H7 F11 GND H8 F12 V H9 CCQH F13 A14 H10 F14 A15 H11 G1 SCK1 or PD3 H12 G2 SCLK or PE2 H13 ...
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... Unlike the TQFP package, most of the GND pins are connected internally in the center of the connection array and act as heat sink for the chip. Therefore, except for GND support the PLL, other GND signals do not support individual subsystems in the chip. 3-6 Freescale Semiconductor, Inc. Table 3-1. Signal List by Ball Number (Continued) Ball Signal Name Signal Name No ...
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... Freescale Semiconductor, Inc. Table 3-2. Signal List by Signal Name Ball Signal Name Signal Name No. A0 N14 A1 M13 A10 H13 A11 H14 A12 G14 A13 G12 A14 F13 A15 F14 A16 E13 A17 E12 A2 M14 A3 L13 A4 L14 A5 K13 A6 K14 A7 J13 A8 J12 A9 J14 ...
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... FC-PBGA Package Description Signal Name 3-8 Freescale Semiconductor, Inc. Table 3-2. Signal List by Signal Name (Continued) Ball Signal Name No. GND F9 GND GND F10 GND GND F11 GND GND G4 GND GND G5 GND GND G6 GND GND G7 GND GND G8 GND GND G9 GND GND G10 ...
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... Freescale Semiconductor, Inc. Table 3-2. Signal List by Signal Name (Continued) Ball Signal Name Signal Name No. MODA C4 MODB A5 MODC C5 MODD A14 NC B14 NC M10 P14 NMI D1 PB0 M5 PB1 P4 PB10 M2 Reserved PB11 J2 Reserved PB12 J3 RESET PB13 L1 PB14 K2 PB15 J1 PB2 N4 PB3 P3 PB4 N3 PB5 P2 PB6 N1 PB7 ...
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... DATUM A THE SEATING PLANE IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS AND E2 DEFINE THE AREA OCCUPIED BY THE DIE. Figure 3-3. DSP56321T Mechanical Information, 196-pin FC-PBGA Package 3-10 Freescale Semiconductor, Inc. CASE 1128F-01 ISSUE A For More Information On This Product, Go to: www.freescale.com Millimeters MIN ...
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... Freescale Semiconductor, Inc. Chapter 4 Design Considerations 4.1 Thermal Design Considerations Equation 1: Equation 2: An estimate of the chip junction temperature, T this equation Where ambient temperature ° package junction-to-ambient thermal resistance °C power dissipation in package D Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance, ...
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... Ensure that capacitor leads and associated printed circuit traces that connect to the chip pins are less than 0.5 inch per capacitor lead. • Use at least a four-layer PCB with two inner layers for 4-2 Freescale Semiconductor, Inc determined by a thermocouple, thermal resistance is T – T )/P ...
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... Freescale Semiconductor, Inc. • Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal. This recommendation particularly applies to the address and data buses as well as the IRQC , IRQD • Consider all device loads as well as parasitic capacitance due to PCB traces when you calculate capacitance ...
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... The phase and frequency jitter performance results are valid only if the input jitter is less than the prescribed values. 4-4 Freescale Semiconductor, Inc. max) value reflects the typical possible switching of the internal CCI ) value reflects the average switching of the internal buses on typical operating conditions. ...
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... Freescale Semiconductor, Inc. Appendix A Power Consumption Benchmark The following benchmark program evaluates DSP56321T power use in a test situation. It enables the PLL, disables the external clock, and uses repeated multiply-accumulate (MAC) instructions with a set of synthetic DSP application data to emulate intensive sustained DSP operation. ...
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... A-2 Freescale Semiconductor, Inc. b #$0,x0 #$0,x1 #$0,y0 #$0,y1 #4,omr ; ebd #60,_end x0,y0,a x:(r0)+,x1 y:(r4)+,y1 x1,y1,a x:(r0)+,x0 y:(r4)+,y0 a,b x0,y0,a x:(r0)+,x1 x1,y1,a y:(r4)+,y0 b1,x:$ff sbr x:0 $262EB9 $86F2FE $E56A5F $616CAC $8FFD75 $9210A $A06D7B $CEA798 $8DFBF1 $A063D6 $6C6657 $C2A544 $A3662D $A4E762 ...
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... Freescale Semiconductor, Inc. dc $EB3B4B dc $2DA928 dc $AB6641 dc $28A7E6 dc $4E2127 dc $482FD4 dc $7257D dc $E53C72 dc $1A8C3 dc $E27540 XDAT_END YDAT_START ; org y:0 dc $5B6DA dc $C3F70B dc $6A39E8 dc $81E801 dc $C666A6 dc $46F8E7 dc $AAEC94 dc $24233D dc $802732 dc $2E3C83 dc $A43E00 dc $C2B639 dc $85A47E dc $ABFDDF dc $F3A2C dc $2D7CF5 dc $E16A8A dc $ECB8FB dc $4BED18 dc $43F371 dc $83A556 dc $E1E9D7 dc $ACA2C4 dc $8135AD ...
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... M_HDSP EQU $9 M_HASP EQU $A M_HMUX EQU $B M_HD_HS EQU $C M_HCSP EQU $D M_HRP EQU $E M_HAP EQU $F A-4 Freescale Semiconductor, Inc. 132,55,0,0,0 mex 1,0 ; Host port GPIO data Register ; Host port GPIO direction Register ; Port C Control Register ; Port C Direction Register ; Port C GPIO Data Register ...
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... Freescale Semiconductor, Inc. ;------------------------------------------------------------------------ ; ; EQUATES for Serial Communications Interface (SCI) ; ;------------------------------------------------------------------------ ; Register Addresses M_STXH EQU $FFFF97 ; SCI Transmit Data Register (high) M_STXM EQU $FFFF96 ; SCI Transmit Data Register (middle) M_STXL EQU $FFFF95 ; SCI Transmit Data Register (low) M_SRXH EQU $FFFF9A ; SCI Receive Data Register (high) M_SRXM EQU $FFFF99 ...
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... SSI Receive Slot Mask Register A M_SSRSA EQU $FFFF ; SSI Receive Slot Mask Register B M_SSRSB EQU $FFFF A-6 Freescale Semiconductor, Inc. ; SSI1 Transmit Data Register 0 ; SSI1 Transmit Data Register 1 ; SSI1 Transmit Data Register 2 ; SSI1 Time Slot Register ; SSI1 Receive Data Register ; SSI1 Status Register ...
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... Freescale Semiconductor, Inc. ;------------------------------------------------------------------------ ; ; EQUATES for Exception Processing ; ;------------------------------------------------------------------------ ; Register Addresses M_IPRC EQU $FFFFFF ; Interrupt Priority Register Core M_IPRP EQU $FFFFFE ; Interrupt Priority Register Peripheral ; Interrupt Priority Register Core (IPRC) M_IAL EQU $7 ; IRQA Mode Mask M_IAL0 EQU 0 ; IRQA Mode Interrupt Priority Level (low) M_IAL1 EQU 1 ...
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... M_DDR1 EQU $FFFFEA ; DMA1 Destination Address Register M_DCO1 EQU $FFFFE9 ; DMA1 Counter M_DCR1 EQU $FFFFE8 ; DMA1 Control Register ; Register Addresses Of DMA2 M_DSR2 EQU $FFFFE7 ; DMA2 Source Address Register A-8 Freescale Semiconductor, Inc. $FFFF8E ; TIMER0 Load Reg ; TIMER0 Compare Register $FFFF8C ; TIMER0 Count Register ; TIMER1 Control/Status Register $FFFF8A ...
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... Freescale Semiconductor, Inc. M_DDR2 EQU $FFFFE6 ; DMA2 Destination Address Register M_DCO2 EQU $FFFFE5 ; DMA2 Counter M_DCR2 EQU $FFFFE4 ; DMA2 Control Register ; Register Addresses Of DMA4 M_DSR3 EQU $FFFFE3 ; DMA3 Source Address Register M_DDR3 EQU $FFFFE2 ; DMA3 Destination Address Register M_DCO3 EQU $FFFFE1 ; DMA3 Counter M_DCR3 EQU $FFFFE0 ...
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... M_BYEN EQU 5 M_BAM EQU 6 M_BPAC EQU 7 M_BNC EQU $F00 ; Number of Address Bits to Compare Mask (BNC0-BNC3) M_BAC EQU $FFF000; Address to Compare Bits Mask (BAC0-BAC11) A-10 Freescale Semiconductor, Inc. $FFFFB6 ; EFCOP Data Base Address $FFFFB7 ; EFCOP Coefficient Base Address $FFFFB8 ; EFCOP Decimation/Channel Register ...
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... Freescale Semiconductor, Inc. ; control and status bits in SR M_CP EQU $c00000; mask for CORE-DMA priority bits in SR M_CA EQU 0 ; Carry M_V EQU 1 ; Overflow M_Z EQU 2 ; Zero M_N EQU 3 ; Negative M_U EQU 4 ; Unnormalized M_E EQU 5 ; Extension M_L EQU 6 ; Limit M_S EQU 7 ; Scaling Bit M_I0 EQU 8 ...
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... I_HC EQU I_VEC+$64 ;----------------------------------------------------------------------- ; EFCOP Filter Interrupts ;----------------------------------------------------------------------- I_FDIIE EQU I_FDOIE EQU ;------------------------------------------------------------------------ ; INTERRUPT ENDING ADDRESS ;------------------------------------------------------------------------ I_INTEND EQU I_VEC+$FF A-12 Freescale Semiconductor, Inc. ; Trap ; Non Maskable Interrupt ; IRQA ; IRQB ; IRQC ; IRQD ; DMA Channel 0 ; DMA Channel 1 ; DMA Channel 2 ; DMA Channel 3 ; DMA Channel 4 ; DMA Channel 5 ; ESSI1 Receive last slot ...
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... Freescale Semiconductor, Inc. Index A ac electrical characteristics 2-4 address bus 1-1 applications iv B benchmark test algorithm A-1 block diagram i bootstrap ROM iii Boundary Scan (JTAG Port) timing diagram 2-31 bus address 1-2 control 1-1 data 1-2 external address 1-4 external data 1-4 ...
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... O off-chip memory iii OnCE module iii Debug request 2-32 On-Chip Emulation (OnCE) module interface 1-17 On-Chip Emulation module iii Index-2 Freescale Semiconductor, Inc. , 1-7 , 1-2 , 2-2 For More Information On This Product, Go to: www.freescale.com on-chip memory iii operating mode select timing 2-11 ...
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... Freescale Semiconductor, Inc. Stop timing 2-7 supply voltage 2-2 Switch mode iii T target applications iv Test Access Port (TAP) iii timing diagram 2-31 Test Clock (TCLK) input timing diagram 2-30 thermal design considerations 4-1 Timer event input restrictions 2- Timers 1-1 1-2 1-16 ...
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... Index Index-4 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...
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... TECHNICAL INFORMATION CENTER: 1-800-521-6274 HOME PAGE: http://www.motorola.com/semiconductors Freescale Semiconductor, Inc. Package Type Pin Count Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. ...