EPF10K10QC208-3N Altera, EPF10K10QC208-3N Datasheet - Page 24

• Manufacturer Part Number: EPF10K10QC208-3N
• Description: IC PLD 576 MACROCELL 60MHZ QFP-208
• Manufacturer: Altera
• Series: FLEX 10Kr

Specifications of EPF10K10QC208-3N

• No. Of Macrocells: 576
• No. Of I/o's: 134
• Global Clock Setup Time: 1.3ns
• Frequency: 60MHz
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To +70°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Asynchronous Preset
An asynchronous preset is implemented as either an asynchronous load,
or with an asynchronous clear. If DATA3 is tied to V
, asserting
CC
LABCTRL1 asynchronously loads a one into the register. Alternatively, the
Altera software can provide preset control by using the clear and
inverting the input and output of the register. Inversion control is
available for the inputs to both LEs and IOEs. Therefore, if a register is
preset by only one of the two LABCTRL signals, the DATA3 input is not
needed and can be used for one of the LE operating modes.
Asynchronous Preset & Clear
When implementing asynchronous clear and preset, LABCTRL1 controls
the preset and LABCTRL2 controls the clear. DATA3 is tied to V
,
CC
therefore, asserting LABCTRL1 asynchronously loads a one into the
register, effectively presetting the register. Asserting LABCTRL2 clears the
register.
Asynchronous Load with Clear
When implementing an asynchronous load in conjunction with the clear,
LABCTRL1 implements the asynchronous load of DATA3 by controlling
the register preset and clear. LABCTRL2 implements the clear by
controlling the register clear; LABCTRL2 does not have to feed the preset
circuits.
Asynchronous Load with Preset
When implementing an asynchronous load in conjunction with preset, the
Altera software provides preset control by using the clear and inverting
the input and output of the register. Asserting LABCTRL2 presets the
register, while asserting LABCTRL1 loads the register. The Altera software
inverts the signal that drives DATA3 to account for the inversion of the
register’s output.
Asynchronous Load without Preset or Clear
When implementing an asynchronous load without preset or clear,
LABCTRL1 implements the asynchronous load of DATA3 by controlling
the register preset and clear.
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Altera Corporation